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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
PM7350 S/UNITM
DUPLEX
S/UNI-DUPLEX
DUAL SERIAL LINK, PHY MULTIPLEXER
DATA SHEET
RELEASED ISSUE 5: APRIL 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
REVISION HISTORY
Issue No. Issue 5
Issue Date April 2000
Originator Phil Walston
Details of Change Updated analog parameters, IDDOP, thermal info and corrected register description typos. Release to production. Updated to incorporate Revision B changes outinled in previous Errata. Change bars highlight specific changes. Changed confidentiality notices for document's public release. Extensive updates throughout First release
Issue 4
February 2000
Phil Walston
Issue 3 Issue 2 Issue 1
June 1999 May, 1999 May, 1998
James Lamothe Jeff Brown Jeff Brown
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
CONTENTS 1 2 3 4 5 6 7 8 9 FEATURES .............................................................................................. 1 APPLICATIONS ....................................................................................... 3 REFERENCES......................................................................................... 4 APPLICATION EXAMPLES ..................................................................... 5 BLOCK DIAGRAM ..................................................................................11 DESCRIPTION ...................................................................................... 12 PIN DIAGRAM ....................................................................................... 14 PIN DESCRIPTION................................................................................ 15 FUNCTIONAL DESCRIPTION............................................................... 45 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10 11 PARALLEL BUS INTERFACE ..................................................... 45 CLOCKED SERIAL DATA INTERFACE ...................................... 57 HIGH-SPEED SERIAL INTERFACE ........................................... 61 CELL BUFFERING AND FLOW CONTROL ............................... 71 TIMING REFERENCE INSERTION AND RECOVERY ............... 75 JTAG TEST ACCESS PORT....................................................... 76 MICROPROCESSOR INTERFACE ............................................ 76 INTERNAL REGISTERS ............................................................. 80 REGISTER MEMORY MAP ........................................................ 80
NORMAL MODE REGISTER DESCRIPTION ....................................... 84 TEST FEATURES DESCRIPTION ...................................................... 170 11.1 11.2 RAM BUILT-IN-SELF-TEST ...................................................... 173 JTAG TEST PORT .................................................................... 177
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
12
OPERATION ........................................................................................ 182 12.1 12.2 12.3 12.4 12.5 MICROPROCESSOR INBAND COMMUNICATION ................. 182 INTERACTION BETWEEN BUS AND LVDS CONFIGURATIONS .................................................................................................. 184 MAXIMUM CELL BIT RATE ...................................................... 193 MINIMUM PROGRAMMING ..................................................... 194 JTAG SUPPORT ....................................................................... 196
13
FUNCTIONAL TIMING......................................................................... 203 13.1 13.2 SCI-PHY/ANY-PHY INTERFACE .............................................. 203 CLOCKED SERIAL DATA INTERFACE .................................... 208
14 15 16 17 18 19
ABSOLUTE MAXIMUM RATINGS ....................................................... 210 D.C. CHARACTERISTICS ....................................................................211 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS..... 215 A.C. TIMING CHARACTERISTICS...................................................... 219 ORDERING AND THERMAL INFORMATION...................................... 226 MECHANICAL INFORMATION............................................................ 227
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
LIST OF REGISTERS REGISTER 0X00: MASTER RESET AND IDENTITY / LOAD PERFORMANCE METERS ................................................................................................ 85 REGISTER 0X01: MASTER CONFIGURATION .............................................. 86 REGISTER 0X02: MASTER INTERRUPT STATUS ......................................... 88 REGISTER 0X03: MISCELLANEOUS INTERRUPT STATUS ......................... 90 REGISTER 0X04: CLOCK MONITOR.............................................................. 92 REGISTER 0X05: SERIAL LINKS MAINTENANCE ......................................... 94 REGISTER 0X06: EXTENDED ADDRESS MATCH (LSB)............................... 96 REGISTER 0X07: EXTENDED ADDRESS MATCH (MSB).............................. 97 REGISTER 0X08: EXTENDED ADDRESS MASK (LSB) ................................. 98 REGISTER 0X09: EXTENDED ADDRESS MASK (MSB) ................................ 99 REGISTER 0X0A: OUTPUT ADDRESS MATCH ........................................... 100 REGISTER 0X0B: CONFIGURATION PINS STATUS.................................... 101 REGISTER 0X0C: SCI-PHY/ANY-PHY INPUT CONFIGURATION 1 ............. 103 REGISTER 0X0D: SCI-PHY/ANY-PHY INPUT CONFIGURATION 2 ............. 105 REGISTER 0X0E: SCI-PHY/ANY-PHY INPUT INTERRUPT ENABLES ........ 107 REGISTER 0X0F: SCI-PHY/ANY-PHY INPUT INTERRUPT STATUS ........... 108 REGISTER 0X10: INPUT CELL AVAILABLE ENABLE (LSB)......................... 109 REGISTER 0X11: INPUT CELL AVAILABLE ENABLE (2ND) ........................ 109 REGISTER 0X12: INPUT CELL AVAILABLE ENABLE (3RD) .........................110 REGISTER 0X13: INPUT CELL AVAILABLE ENABLE (MSB).........................110 REGISTER 0X14: SCI-PHY/ANY-PHY OUTPUT CONFIGURATION..............112 REGISTER 0X15: SCI-PHY/ANY-PHY OUTPUT POLLING RANGE ..............115
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
REGISTERS 0X18, 0X1A: RXD1, RXD2 BIT ORIENTED CODE RECEIVER ENABLE................................................................................................116 REGISTER 0X19, 0X1B: RXD1, RXD2 RECEIVE BIT ORIENTED CODE STATUS ................................................................................................117 REGISTERS 0X1D, 0X1F: TXD1, TXD2 TRANSMIT BIT ORIENTED CODE.118 REGISTER 0X20: MICROPROCESSOR CELL BUFFER INTERRUPT..........119 REGISTER 0X21: MICROPROCESSOR INSERT FIFO CONTROL.............. 121 REGISTER 0X22: MICROPROCESSOR EXTRACT FIFO CONTROL .......... 122 REGISTER 0X23: MICROPROCESSOR INSERT FIFO READY................... 124 REGISTER 0X24: MICROPROCESSOR EXTRACT FIFO READY ............... 125 REGISTER 0X25: INSERT CRC-32 ACCUMULATOR (LSB)......................... 126 REGISTER 0X26: INSERT CRC-32 ACCUMULATOR (2ND)......................... 126 REGISTER 0X27: INSERT CRC-32 ACCUMULATOR (3RD)......................... 126 REGISTER 0X28: INSERT CRC-32 ACCUMULATOR (MSB) ........................ 127 REGISTER 0X29: EXTRACT CRC-32 ACCUMULATOR (LSB) ..................... 128 REGISTER 0X2A: EXTRACT CRC-32 ACCUMULATOR (2ND) .................... 128 REGISTER 0X2B: EXTRACT CRC-32 ACCUMULATOR (3RD) .................... 128 REGISTER 0X2C: EXTRACT CRC-32 ACCUMULATOR (MSB).................... 129 REGISTER 0X2D: MICROPROCESSOR CELL DATA................................... 130 REGISTER 0X30: RXD1 EXTRACT FIFO CONTROL ................................... 131 REGISTER 0X31: RXD1 EXTRACT FIFO INTERRUPT STATUS.................. 132 REGISTER 0X34: RXD2 EXTRACT FIFO CONTROL ................................... 133 REGISTER 0X35: RXD2 EXTRACT FIFO INTERRUPT STATUS.................. 134 REGISTER 0X3C: RECEIVE LOGICAL CHANNEL FIFO CONTROL............ 135
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
REGISTER 0X3D:RECEIVE LOGICAL CHANNEL FIFO INTERRUPT STATUS ............................................................................................................. 137 REGISTERS 0X40, 0X50: RXD1, RXD2 HIGH-SPEED SERIAL CONFIGURATION ............................................................................... 138 REGISTERS 0X41, 0X51: RXD1, RXD2 HIGH-SPEED SERIAL CELL FILTERING CONFIGURATION/STATUS ............................................. 140 REGISTERS 0X42, 0X52: RXD1, RXD2 HIGH-SPEED SERIAL INTERRUPT ENABLES ............................................................................................ 142 REGISTERS 0X43,0X53: RXD1, RXD2 HIGH-SPEED SERIAL INTERRUPT STATUS ............................................................................................... 144 REGISTERS 0X44, 0X54: RXD1, RXD2 HIGH-SPEED SERIAL HCS ERROR COUNT ................................................................................................ 146 REGISTERS 0X45, 0X55: RXD1, RXD2 HIGH-SPEED SERIAL CELL COUNTER (LSB) ................................................................................. 147 REGISTERS 0X46, 0X56: RXD1, RXD2 HIGH-SPEED SERIAL CELL COUNTER ........................................................................................... 147 REGISTERS 0X47, 0X57: RXD1, RXD2 HIGH-SPEED SERIAL CELL COUNTER (MSB) ................................................................................ 148 REGISTER 0X5C: TRANSMIT LOGICAL CHANNEL FIFO CONTROL ......... 149 REGISTER 0X5D: TRANSMIT LOGICAL CHANNEL FIFO INTERRUPT STATUS150 REGISTER 0X5E: TRANSMIT LOGICAL CHANNEL FIFO DEPTH............... 151 REGISTER 0X60: TRANSMIT HIGH-SPEED SERIAL CONFIGURATION .... 152 REGISTER 0X61: TRANSMIT HIGH-SPEED SERIAL CELL COUNT STATUS ............................................................................................................. 154 REGISTER 0X62: TRANSMIT HIGH-SPEED SERIAL CELL COUNTER (LSB) ............................................................................................................. 155 REGISTER 0X63: TRANSMIT HIGH-SPEED SERIAL CELL COUNTER ...... 155 REGISTER 0X64: TRANSMIT HIGH-SPEED SERIAL CELL COUNTER (MSB) ............................................................................................................. 156
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
REGISTER 0X68: RECEIVE SERIAL INDIRECT CHANNEL SELECT .......... 157 REGISTER 0X69: RECEIVE SERIAL INDIRECT CHANNEL CONFIGURATION ............................................................................................................. 159 REGISTER 0X6A: RECEIVE SERIAL INDIRECT CHANNEL INTERRUPT ENABLES ............................................................................................ 161 REGISTER 0X6B: RECEIVE SERIAL INDIRECT CHANNEL INTERRUPT AND STATUS ............................................................................................... 162 REGISTER 0X6C: RECEIVE SERIAL INDIRECT CHANNEL HCS ERROR COUNT ................................................................................................ 164 REGISTER 0X6D: RECEIVE SERIAL LCD COUNT THRESHOLD ............... 165 REGISTER 0X70: TRANSMIT SERIAL INDIRECT CHANNEL SELECT ....... 166 REGISTER 0X71:TRANSMIT SERIAL INDIRECT CHANNEL DATA ............. 167 REGISTER 0X74:TRANSMIT SERIAL ALIGNMENT CONTROL ................... 169 REGISTER 0X80: MASTER TEST ................................................................. 171 REGISTER 0X83: MISCELLANEOUS TEST ................................................. 172
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
LIST OF FIGURES FIG. 1 TYPICAL TARGET APPLICATION ........................................................... 5 FIG. 2 THREE STAGE MULTIPLEX ARCHITECTURE....................................... 7 FIG. 3 CLOCK AND DATA PHY INTERFACE ..................................................... 8 FIG. 4 S/UNI-DUPLEX TO S/UNI-DUPLEX APPLICATIONS............................ 10 FIG. 5 S/UNI-DUPLEX TO S/UNI-DUPLEX PROTECTION SWITCHING ........ 10 FIG. 6 EIGHT BIT SCI-PHY/UTOPIA/ANY-PHY CELL FORMAT...................... 56 FIG. 7 SIXTEEN BIT SCI-PHY/UTOPIA/UTOPIA CELL FORMAT.................... 57 FIG. 8 CELL DELINEATION STATE DIAGRAM................................................ 59 FIG. 9 HIGH-SPEED SERIAL LINK DATA STRUCTURE ................................. 62 FIG. 10 DATAPATH LOOPBACK ...................................................................... 66 FIG. 11 MICROPROCESSOR CELL FORMAT ................................................. 79 FIG. 12 INPUT OBSERVATION CELL (IN_CELL) .......................................... 179 FIG. 13 OUTPUT CELL (OUT_CELL)............................................................. 180 FIG. 14 BIDIRECTIONAL CELL (IO_CELL).................................................... 180 FIG. 15 LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS ....... 181 FIG. 16 BOUNDARY SCAN ARCHITECTURE ............................................... 197 FIG. 17 TAP CONTROLLER FINITE STATE MACHINE ................................. 199 FIG. 18 SCI-PHY INTERFACE, INPUT BUS SLAVE TRANSFER TIMING..... 203 FIG. 19 SCI-PHY INTERFACE, INPUT BUS MASTER TRANSFER TIMING . 204 FIG. 20 ANY-PHY INTERFACE, INPUT BUS SLAVE TRANSFER TIMING.... 205 FIG. 21 SCI-PHY INTERFACE, OUTPUT BUS SLAVE TRANSFER TIMING. 206 FIG. 22 SCI-PHY INTERFACE, OUTPUT BUS MASTER TRANSFER TIMING 207
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
FIG. 23 ANY-PHY INTERFACE, OUTPUT BUS SLAVE TRANSFER TIMING 208 FIG. 24 CLOCKED SERIAL DATA TRANSMIT INTERFACE .......................... 208 FIG. 25 CLOCKED SERIAL DATA TRANSMIT INTERFACE, 1 BIT GAP ...... 209 FIG. 26 CLOCKED SERIAL DATA TRANSMIT INTERFACE, 8 BIT GAP ....... 209 FIG. 27 CLOCKED SERIAL DATA RECEIVE INTERFACE............................. 209 FIG. 28: MICROPROCESSOR INTERFACE READ TIMING .......................... 216 FIG. 29: MICROPROCESSOR INTERFACE WRITE TIMING ........................ 218 FIG. 30: RSTB TIMING ................................................................................... 219 FIG. 31: INGRESS SCI-PHY/ANY-PHY INTERFACE TIMING........................ 220 FIG. 32: EGRESS SCI-PHY/ANY-PHY INTERFACE TIMING......................... 221 FIG. 33: CLOCKED SERIAL DATA INTERFACE ............................................ 222 FIG. 34: JTAG PORT INTERFACE TIMING.................................................... 224
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
LIST OF TABLES TABLE 1 SIGNAL NAME CROSS-REFERENCE ............................................. 46 TABLE 2 EIGHT BIT SCI-PHY/UTOPIA BUS MASTER, INPUT CONFIGURATION ............................................................................................ 48 TABLE 3 SIXTEEN BIT SCI-PHY/UTOPIA BUS MASTER, INPUT CONFIGURATION ............................................................................................ 48 TABLE 4 EIGHT BIT SCI-PHY/UTOPIA BUS MASTER, OUTPUT CONFIGURATION ............................................................................................ 49 TABLE 5 SIXTEEN BIT SCI-PHY/UTOPIA BUS MASTER, OUTPUT CONFIGURATION ............................................................................................ 49 TABLE 6 EIGHT BIT SCI-PHY/UTOPIA BUS SLAVE, INPUT CONFIGURATION 50 TABLE 7 SIXTEEN BIT SCI-PHY/UTOPIA BUS SLAVE, INPUT CONFIGURATION ............................................................................................ 50 TABLE 8 EIGHT BIT SCI-PHY/UTOPIA BUS SLAVE, OUTPUT CONFIGURATION ............................................................................................ 51 TABLE 9 SIXTEEN BIT SCI-PHY/UTOPIA BUS SLAVE, OUTPUT CONFIGURATION ............................................................................................ 52 TABLE 10 SCI-PHY/UTOPIA AND ANY-PHY COMPARISON, INGRESS DIRECTION ...................................................................................................... 53 TABLE 11 EIGHT BIT ANY-PHY BUS SLAVE, INPUT CONFIGURATION ....... 53 TABLE 12 SIXTEEN BIT ANY-PHY BUS SLAVE, INPUT CONFIGURATION .. 54 TABLE 13 SCI-PHY/UTOPIA AND ANY-PHY COMPARISON, EGRESS DIRECTION ...................................................................................................... 54 TABLE 14 EIGHT BIT ANY-PHY BUS SLAVE, OUTPUT CONFIGURATION... 55 TABLE 15 SIXTEEN BIT SCI-PHY/UTOPIA BUS SLAVE, OUTPUT CONFIGURATION ............................................................................................ 55 TABLE 16 PREPENDED FIELDS..................................................................... 62
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
TABLE 17 ASSIGNED BIT ORIENTED CODES .............................................. 69 TABLE 18: BOUNDARY SCAN REGISTER ................................................... 177 TABLE 19 LVDS LINK 59 BYTE CELL CONFIGURATIONS .......................... 188 TABLE 20 LVDS LINK 58 BYTE CELL CONFIGURATIONS .......................... 188 TABLE 21 LVDS LINK 57 BYTE CELL CONFIGURATIONS .......................... 190 TABLE 22 LVDS LINK 61 BYTE CELL CONFIGURATIONS .......................... 192 TABLE 23 LVDS LINK 59 BYTE CELL CONFIGURATIONS WITH CRC ....... 192
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
1
FEATURES * Integrated analog/digital device that interfaces a high-speed parallel bus to a high speed Low Voltage Differential Signal (LVDS) serial link with optional 1:1 protection. For framers or modems without Utopia bus interfaces the S/UNI-DUPLEX provides cell delineation (I.432) across 16 clock and data (bit serial) interfaces. Fault detection, redundancy, protection switching, and inserting/removing cards while the system is running (hot swap). Interface to other S/UNI-DUPLEX or S/UNI-VORTEX, to satisfy a full set of system level requirements for backplane interconnect: * * * * Transports user data by providing the inter-card data-path. Inter-processor communication by providing an integrated inter-card control channel. Exchanges flow control information (back-pressure) to prevent data loss. Provides embedded command and control signals across the backplane: system reset, error indications, protection switching commands, etc. Clock/timing distribution (system clocks as well as reference clocks such as 8 kHz timing references).
*
* *
* * * * *
When used as a parallel bus slave device, can be configured to share the bus with other S/UNI-DUPLEX bus slave devices. Can interface to another S/UNI-DUPLEX device (via a single LVDS link) to create a simple point-to-point "Utopia bus extension" capability. Can interface to two S/UNI-DUPLEX devices to create a 1:1 protected bus extension. Interworks with PM7351 S/UNI-VORTEX devices to implement a point-tomultipoint serial backplane architecture, with optional 1:1 protection of the common card. In the LVDS receive direction: selects traffic from the LVDS link marked active and demultiplexes the individual cell streams to the appropriate PHY device.
*
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
*
Cell read/write to both LVDS links available through the processor port. Provides optional hardware assisted CRC32 calculation across cells to support an embedded inter-processor communication channel across the LVDS links. Requires no external memories. Standard 5 pin P1149.1 JTAG test port. Low-power, 3.3V CMOS technology. 160-pin high-performance plastic ball grid array (PBGA) package.
* * * *
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
2
APPLICATIONS * * * * * Single shelf or multi-shelf Digital Subscriber Loop Access Multiplexer (DSLAM). ATM, frame relay, IP switch. Multiservice access multiplexer. Universal Mobile Telecommunication System (UMTS) wireless base stations. 16 channel cell delineation (I.432 transmission convergence processing).
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
3
REFERENCES * * * PMC-Sierra; "Saturn Compatible Interface For ATM PHY Layer And ATM Layer Devices, Level 2"; PMC-940212; Dec. 8, 1995 ATM Forum, "Universal Test & Operations PHY Interface for ATM (UTOPIA), Level 2", Version 1.0, af-phy-0039.000, June 1995 PMC-Sierra; "Saturn Interface Specification And Interoperability Framework For Packet And Cell Transfer Between Physical Layer And Link Layer Devices", PMC-980902, Draft Draft American National Standard for Telecommunications T1.413 Issue 2, "Network and Customer Installation Interfaces - Asymmetric Digital Subscriber Line (ADSL) Metallic Interface", ANSI T1.413-1998, November 1998 ITU-T Recommendation I.432.1, "B-ISDN user-network interface - Physical layer specification: General characteristics", 08/96
*
*
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
4
APPLICATION EXAMPLES When designing communication equipment such as access switches, multiplexers, wireless base stations, and base station controllers the equipment architect is faced with a common problem: how to efficiently connect a large number of lower speed ports to a small number of high speed ports? Typically, a number of line-side ports (analog modems, xDSL modems ATM PHYs, or RF modems) are terminated on each line card. Numerous line cards are then slotted into one or more shelves and backplane traces or inter-shelf cables are used to connect the line cards to a centralized (often 1:1 protected) common card, hereafter referred to as the core card. The core card normally includes one or more high speed WAN up-link ports that transport traffic to and from a high speed broadband network. A block diagram of a 1:1 redundant system is shown in Fig. 1. Fig. 1 Typical Target Application
Modem or PHY Modem or PHY Modem or PHY Line Card #1 S/UNIDUPLEX S/UNIVORTEX Policing OA&M Buffering Discard Scheduling WAN up-link
OA&M
WAN Card
Modem or PHY Modem or PHY Modem or PHY
Line Card #N S/UNIDUPLEX
S/UNIVORTEX
Policing OA&M
Buffering Discard Scheduling
OA&M
WAN up-link
WAN Card
In this type of equipment the majority (perhaps all) user traffic goes from WAN port to line port, or from line port to WAN port. Although the individual ports on the line cards are often relatively low speed interfaces such as T1, E1, or xDSL, there may be many ports per line card and many line cards per system, resulting in hundreds or even thousands of lines terminating on a single WAN up-link. In the upstream direction (from line card to WAN up-link), the equipment must have capacity to buffer and intelligently manage bursts of upstream traffic simultaneously from numerous line cards.
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
In the downstream direction the equipment must handle a similar issue, the "big pipe feeding little pipe" problem. When a large burst of traffic destined for a single line port is received at the high speed WAN port it must be buffered and managed as it queues up waiting for the much lower speed line port to clear. The line cards are always the most numerous cards in this type of equipment. An individual line card, even if it terminates a few dozen low speed ports, does not generate or receive enough traffic to justify putting complex buffering and traffic management devices on it. The ideal architecture has low cost "dumb" line cards and a feature rich, "smart" core card. In order to enhance fault tolerance, the architecture should also inherently support 1:1 protection using a redundant core card and WAN up-link without significantly increasing line card complexity. A system architecture that keeps buffering and traffic management off the line card with typically exhibit the following features: 1. Connection setup is simpler both in terms of programming and during execution because there is minimal or no requirement for line intervention during the connection setup process. 2. In-service feature upgrades are simpler because feature complexity is limited to the common equipment. 3. Component costs are reduced, while system reliability increases due to reduced component count. In this type of architecture there are often three stages of signal concentration or multiplexing, as shown in Fig 2.
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Fig. 2 Three Stage Multiplex Architecture
Modem Modem Modem Line Card #1
S/UNIDUPLEX
Modem Modem Modem
Line Card #2
S/UNIDUPLEX
S/UNIVORTEX
S/UNIVORTEX
Policing OA&M
Buffering Discard Scheduling
OA&M WAN Card
WAN up-link
Modem Modem Modem
Line Card #N
S/UNIDUPLEX
The first stage resides on the line card and spans only those ports physically terminated by that card. Since it is confined to a single card, this first stage of multiplexing readily lends itself to the simple parallel bus based multiplex topology implemented by the S/UNI-DUPLEX. The second stage of concentration occurs between the core card(s) and the line cards, including line cards that are on a separate shelf. This second stage is best served by a redundant serial point-to-point technology. The third stage of multiplexing is optional and resides on the core card. This third stage is used in systems with a large number of line cards that require several devices to terminate the second stage of aggregation. Since the third stage of aggregation is confined to the core card, it lends itself readily to a parallel bus implementation. This three stage approach is implemented directly by the S/UNI-DUPLEX and its sister device, the S/UNI-VORTEX. The S/UNI-DUPLEX acts as the line card's bus master. It implements the first stage of multiplexing by routing traffic from the PHYs and transmitting the traffic simultaneously over two high speed (200 Mbps) serial 4-wire LVDS links. One serial link attaches to the active core card, the other to the standby core card. In the downstream direction the S/UNI-DUPLEX demultiplexes traffic from the active core card's LVDS serial link and routes this traffic to the appropriate PHYs. If the active core card (or its LVDS link) should fail, protection switching commands embedded in the spare LVDS link will direct the S/UNI-DUPLEX to start receiving its traffic from this spare link.
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
The S/UNI-VORTEX resides on the core card and terminates up to 8 LVDS links connected to 8 S/UNI-DUPLEX devices. The S/UNI-VORTEX implements the second stage of multiplexing. More than one S/UNI-VORTEX will be required if more than 8 links are required - as will be the case for a system with more than 8 line cards. The S/UNI-VORTEX device(s) share a high speed parallel bus with the core card's traffic management and OA&M layers, as implemented by devices such as PMC-Sierra's S/UNI-APEX and the S/UNI-ATLAS. Some applications use framer or modem devices without integrated I.432 processing1 normally support a clock and data interface, and rely on external circuitry to detect and generate ATM cell framing and overhead. To support these applications, the S/UNI-DUPLEX provides a clock and data mode2. In this mode, the input/output pins that normally interface to the Utopia bus are configured to support up to 16 clock and data serial interfaces. This type of line card is shown in Fig. 3. The I.432 processing is transparent to the far end device, which implies that a single S/UNI-VORTEX can simultaneously interface to line cards that implement the Utopia bus and to line cards that use clock and data interfaces. Fig. 3 Clock and Data PHY Interface
Line Card
Rx Clock Rx Data
Modem #1
Tx Clock Tx Data
S/UNIDUPLEX
4-wire LVDS
Modem #16
Some PHY devices provide a 3-line interface consisting of clock, data, and overhead indication. For these PHYs external circuitry can be used to adapt to the S/UNI-DUPLEX's 2-line interface.
1 2
Cell delineation, payload scrambling-descrambling, idle cell generation/discard, etc.. Either Utopia mode or clock and data mode can be selected, but not both at once.
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
In the clock and data receive direction the S/UNI-DUPLEX performs bit level ATM cell delineation function. In the transmit direction the S/UNI-DUPLEX can operate in either bit or frame aligned mode. In frame mode (also called byte aligned mode) the two wire transmit interface continuously monitors for gaps in the transmit clock to determine where the frame or byte alignment should occur. The circuitry assumes that when a gap in the transmit clock is detected this is either the framing bit position (e.g. the DS-1 framing bit) or an overhead byte (e.g. ADSL modem). In either case the next clock period after the gap is assumed to represent the byte alignment position. In the multiplexer application discussed previously the S/UNI-DUPLEX's LVDS interfaces are connected to one or two S/UNI-VORTEX devices. It is also possible to interface S/UNI-DUPLEX to S/UNI-DUPLEX via the LVDS link. Since the S/UNI-DUPLEX bus interface can be configured in several ways (clock and data, 8/16 bits bus master, 8/16 bit bus slave) there are various applications where two S/UNI-DUPLEX devices can be used "back-to-back" in order to perform one or more of the following functions: 1. Interfacing a bus master device to another bus master. 2. Interfacing a bus slave device to another bus slave. 3. Converting between 8 bit and 16 bit buses. 4. Off card or off shelf bus extension. 5. Cell delineation (I.432 processing). 6. Protection switching. Examples of these types of configurations are shown in Fig. 4 and Fig. 5.
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Fig. 4 S/UNI-DUPLEX to S/UNI-DUPLEX Applications Bus master 8 bit bus S/UNIDUPLEX
LVDS
S/UNIDUPLEX 16 bit bus
Bus master
Example of on-card bus conversion: 8 bit bus master to 16 bit bus master
Bus master
S/UNIDUPLEX
LVDS
S/UNIDUPLEX
Bus slave
Example of basic bus extension between cards
Framer #1 Framer #2 S/UNIDUPLEX
LVDS
S/UNIDUPLEX
Bus master
Framer # 16
Fig. 5 S/UNI-DUPLEX to S/UNI-DUPLEX Protection Switching
...
Clock + data 8/16 bit bus Example of on-card I.432 processing
Bus master
S/UNIDUPLEX
S/UNIDUPLEX
Bus slave
Bus master
S/UNIDUPLEX
S/UNIDUPLEX
Bus slave
Example of protection switching between cards
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10
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
5
BLOCK DIAGRAM Although separated to improve clarity, many signals in the following diagram share physical package pins. The use of the SCI-PHY/Any-PHY interfaces and the clocked serial data interfaces is mutually exclusive.
RS TOB RC LK RX8K TX8 K
SC IA NY O BU S8 OA N YPH Y OMAS TE R OEN B OADD R[4:0] OAVA LID ODAT[15:0] OPR TY OSOC OS X OFCLK OCA
SCI-PHY Transm it Mas ter/ Receive Slav e
LTXD [15 :0] LTXC [15 :0] LR XD [15:0] LR XC [15:0] IBUS 8 IA N YP H Y IMA STER IEN B IAD DR [4:0] IAV AL ID ID A T[15 :0] IP R TY IS OC IS X IFC LK IC A A[7:0 ] RDB W RB C SB ALE IN TB R STB D [7:0] to all blocks MicroProcessor Interface
Elastic Store
Tim e-Sliced AT M Trans m ission Convergence
per-PH Y buffers Cell Processor per-PH Y buffers
R XD1+ R XD1TXD 1+ TXD 1R XD2+ R XD2TXD 2+ TXD 2-
SCI-PHY Rec eive Master/ Transm it Slave
2 Cell Buffer 4 C ell FIFO
Clock Synthesis
REFC LK
TD O JTAG Test Access Port TD I TC K TMS TR S TB
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11
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
6
DESCRIPTION The PM7350 S/UNI-DUPLEX is a monolithic integrated circuit typically used with its sister device, the S/UNI-VORTEX, to implement a point-to-point serial backplane interconnect architecture. The primary role of the S/UNI-DUPLEX is to interface to up to 32 devices (typically framers or PHYs) and transfer 52-56 byte data cells in serial format to/from a backplane. Devices interface to the S/UNI-DUPLEX via an 8 or 16-bit SCI-PHY/Utopia/Any-PHY bus, or optionally via a 16 port clock and data interface. Each S/UNI-DUPLEX can connect to two 100 to 200 Mb/s Low Voltage Differential Signal (LVDS) serial links. A microprocessor port provides access to internal configuration and monitoring registers. The microprocessor port may also be used to insert and extract cells in support of an embedded microprocessor communication channel. BUS INTERFACE: One of four modes can be selected:
*
8 or 16 bit, Utopia L2 bus master operating at up to 33 MHz bus clock frequency. Also supports PMC-Sierra's SCI-PHY bus standard which is compatible with Utopia L2 but allows extended length cells and supports an additional bus address signal in order to support 32 PHY devices rather than Utopia's 31. See Table 1 for a comparison of these bus standards. 16 port, 4 pin clocked serial data interface (Tx, TxClk, Rx, RxClk), with integrated I.432 ATM cell delineation operating at up to 52 MHz serial clock frequency. 8 or 16 bit, SCI-PHY/Utopia bus slave operating at up to 52 MHz bus clock frequency. The slave input port presents itself as 32 addressable logical channels. The slave output port appears as a single addressable channel carrying the multiplexed traffic from up to 32 logical channels where each cell's channel number can optionally be embedded in the H5 header field (Utopia bus mode) or indicated in a cell prepend (SCI-PHY bus mode). 8 or 16 bit, Any-PHY bus slave (bus protocol compatible with the PM7351 S/UNI-VORTEX) operating at up to 52 MHz bus clock frequency. The slave input port presents itself as 32 addressable logical channels. The slave output port appears as a single addressable channel carrying the multiplexed traffic from up to 32 logical channels. In both directions each cell's logical channel number is indicated in a cell prepend.
*
*
*
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12
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
LVDS INTERFACES (both directions):
*
Dual 4-wire LVDS serial transceivers each operating at 100 to 200 Mbps across PCB or backplane traces, or across up to 10 meters of 4-wire twisted pair cabling for inter-shelf communications. Full integrated LVDS clock synthesis and recovery. No external analog components are required. Usable bandwidth (excludes system overhead) of 186 Mbps.
* *
LVDS TRANSMIT DIRECTION
* * * *
Simple round robin multiplex of up to 32 PHYs (or 16 clock and data interfaces) plus the microprocessor port's cell transfer buffer. Multiplexed cell stream broadcast to both LVDS simultaneously. 6 bit port ID prepended to each cell for use by ATM layer to identify cell source (1 of 32 PHYs or processor). Back-pressure provided by far end (active link only) to prevent overflow of far end receiver.
LVDS RECEIVE DIRECTION
*
Cells received from the active LVDS link are forwarded to the appropriate PHY, bit serial interface, or the microprocessor port as specified by a 6 bit port ID added to each cell at the far end device. The LVDS link marked as "spare" is monitored for errors, PHY cells are discarded, microprocessor port cells are accepted. Individual PHY and microprocessor FIFO back-pressure indications are sent to the far end to prevent FIFO overflows. Per stream back-pressure prevents head-of-line blocking.
* *
MICROPROCESSOR INTERFACE
* * *
8 bit data bus, 8 bit address bus. Provides read/write access to all configuration and status registers. Provides CRC32 calculation and cell transfer registers to support an embedded microprocessor to microprocessor communication channel over the LVDS link.
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13
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
7
PIN DIAGRAM The S/UNI-DUPLEX is packaged in a 160-pin plastic ball grid array (PBGA) package having a body size of 15 mm by 15 mm and a ball pitch of 1.00 mm.
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
TRSTB
TDI
A[2]
RSTB
A[6]
RDB
BIAS
IMASTER LTXD[15]
IADDR[3] LRXC[15]
IADDR[1] LRXD[14]
ICA LRXC[13]
RSTOB
B
TX8K
TCK
TMS
A[0]
A[4]
A[5]
ALE
INTB
IAVALID LTXC[15]
VSS
IENB LRXD[13]
VDD
IPRTY LTXD[13]
IDAT[15] LTXC[13]
C
D[7]
VDD
VSS
A[1]
VSS
A[7]
VSS
SCIANY
IBUS8 LTXD[14]
VDD
IADDR[0] LRXC[14]
VSS
IDAT[14] LTXD[12]
IDAT[13] LTXC[12]
D
D[4]
D[6]
D[5]
A[3]
VDD
WRB
CSB
VSS
IADDR[4] LRXD[15]
IADDR[2] LTXC[14]
VSS
IDAT[11] LRXC[12]
IDAT[12] LRXD[12]
IDAT[10] LTXD[11]
E
VDD
RX8K
VSS
RCLK
IDAT[7] LRXC[11]
IDAT[8] LRXD[11]
VDD
IDAT[9] LTXC[11]
F
D[0]
D[2]
D[1]
D[3]
IFCLK LTXC[9]
VDD
IDAT[6] LTXD[10]
IDAT[5] LTXC[10]
G
RXD1+
RXD1-
RES
TAVD
GND
GND
IDAT[3] LTXD[8]
IDAT[1] LTXD[7]
VSS
IDAT[4] LTXD[9]
H
TXD1+
TXD1-
TAVS
RESK
GND
GND
ISX LTXC[6]
IDAT[2] LTXC[8]
ISOC LTXD[6]
IDAT[0] LTXC[7]
J
RXD2+
RXD2-
RAVS
RAVD
ODAT[15] LRXC[10]
VSS
OPRTY LRXD[10]
IANYPHY LTXD[5]
K
TXD2+
TXD2-
TAVS
TAVD
VSS
ODAT[14] LRXD[9]
ODAT[13] LRXC[9]
VDD
L
ATP0
ATP1
CAVS
CAVD
OADDR[1] LRXD[0]
VDD
VSS
OSOC LRXD[3]
ODAT[2] LRXD[4]
ODAT[4] LRXC[6]
VDD
ODAT[12] LTXC[5]
ODAT[11] LRXD[8]
VDD
M
QAVS
QAVD
VDD
OMASTER LTXD[1]
OADDR[3] LTXC[1]
OAVALID LRXD[1]
VSS
VDD
VSS
OANYPHY LTXD[2]
ODAT[5] LRXD[6]
ODAT[9] LTXC[4]
VSS
ODAT[10] LRXC[8]
N
VSS
VDD
Unused LTXD[0]
VSS
OADDR[2] LTXC[0]
OADDR[4] LRXC[1]
OCA LRXC[2]
ODAT[1] LRXC[4]
ODAT[3] LRXD[5]
OFCLK LRXC[5]
ODAT[6] LRXC[7]
VDD
ODAT[8] LTXC[3]
Unused LTXD[3]
P
TDO
REFCLK
OADDR[0] LRXC[0]
VSS
OENB LRXD[2]
OSX LRXC[3]
ODAT[0] LTXC[2]
VDD
VSS
OBUS8 LTXD[4]
VSS
ODAT[7] LRXD[7]
BOTTOM VIEW
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
8
PIN DESCRIPTION Ball Name RXD1+ RXD1RXD2+ RXD2Ball No. G14 G13 J14 J13
Type Diff. LVDS Input
Function High Speed LVDS Links The high-speed receive data (RXD1+/-, RXD2+/-) inputs present NRZ data from a serial backplane. Two pairs are provided for redundancy. The active link may be chosen by the local microprocessor or determined by a simple handshake. RXD1+/- and RXD2+/- are truly differential inputs offering superior common-mode noise rejection. They have sufficient sensitivity and common-mode range to support LVDS signals.
TXD1+ TXD1TXD2+ TXD2-
Diff. LVDS Output
H14 H13 K14 K13
The transmit differential data (TXD1+/-, TXD2+/-) outputs present NRZ encoded data to a serial backplane. These outputs are open drain current sinks which interface directly with twisted-pair cabling or board interconnect. Edge rates are controlled to minimize radiated emissions. Both differential links carry identical traffic except the exact phase relationship is not guaranteed.
REFCLK
Input
P12
The reference clock input (REFCLK) must provide a jitter-free reference clock. It is used as the reference clock by both clock recovery and clock synthesis circuits. Any jitter below 1 MHz is transferred directly to the TXD1+/- and TXD2+/outputs. The high-speed serial interface bit rate is eight times the REFCLK frequency. A 4.75k 1% resistor must be connected between these two pins to achieve the correct LVDS output signal levels. The Analog Test Points (ATP) are provided for production test purposes. In mission mode they are high impedance and should be connected to ground.
RES RESK ATP0 ATP1
Analog
G12 H11 L14 L13
Analog
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name TX8K
Type Input
Ball No. B14
Function High Speed LVDS Links The transmit 8 kHz timing reference (TX8K) input allows a traceable signal to be transmitted to the far end of the high-speed serial links via TXD1+/- and TXD2+/-. A rising edge on TX8K is encoded in the next cell transmitted. Although TX8K is targeted at a typical need of transporting an 8 kHz signal, its frequency is not constrained to 8 kHz. Any frequency less than the cell rate is permissible.
RX8K
Output
E13
The receive 8 kHz timing reference (RX8K) output presents the timing extracted from one of the receive high-speed serial links, RXD1+/- or RXD2+/-. The rising edge of RX8K is accurate to the nearest byte boundary of the high-speed serial link; therefore, a small amount of jitter is present. At a link rate of 155.52 Mb/s, the jitter is 63ns peak-topeak. Pulses on RX8K are always 16 high-speed serial link bit periods wide (two REFCLK periods).
RCLK
Output
E11
The Recovered Clock (RCLK) output presents the byte clock for the active receive high-speed serial link. The RCLK frequency shall be 0.125 of the RXD1+/- or RXD2+/- bit rate. Due to the digital clock recovery technique employed, jitter is introduced as 12.8 ns phase steps. If the active link is changed, RCLK can not be guaranteed to be glitch free. Because of these two factors, RCLK must be cleaned up by a PLL before it is suitable for use as a timing reference.
Clocked Data Serial Interface
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name SCIANY
Type Input
Ball No. C7
Function High Speed LVDS Links The SCI-PHY/Any-PHY Interface (SCIANY) input selects the type of PHY device interface. If SCIANY is a logic high, the S/UNI-DUPLEX will be configured to communicate to the PHY devices via a shared SCI-PHY Level 2, Utopia L2, or Any-PHY cell bus. If SCIANY is a logic low, each PHY device has a dedicated clocked bit serial interface. The two types of interfaces share common package pins. Failure to present the correct logic level on this signal for the application may result in damage to the S/UNI-DUPLEX or the PHY devices. When SCIANY is logic high, LTXD[3] and LTXD[0] become inputs and need to be tied to VDD or VSS through a pull up or a pull down.
LRXD[15] LRXD[14] LRXD[13] LRXD[12] LRXD[11] LRXD[10] LRXD[9] LRXD[8] LRXD[7] LRXD[6] LRXD[5] LRXD[4] LRXD[3] LRXD[2] LRXD[1] LRXD[0]
D6 (SCIANY= A4 B4 0) D2 E3 J2 K3 L2 P2 M4 N6 L6 L7 P9 M9 L10
Input
The low-speed receive data (LRXD[15:0]) inputs provide data from individual modem channels. The data streams must carry contiguous ATM cells with valid HCS (Header Check Sequence) bytes. LRXD[n] can be clocked either by the rising or falling edge of the corresponding LRXC[n] input, depending on the value of the LRXCINV bit of the Master Configuration register. By default, the rising edge is used. These inputs are only active if the SCIANY input is a logic low.
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17
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name LRXC[15] LRXC[14] LRXC[13] LRXC[12] LRXC[11] LRXC[10] LRXC[9] LRXC[8] LRXC[7] LRXC[6] LRXC[5] LRXC[4] LRXC[3] LRXC[2] LRXC[1] LRXC[0] LTXD[15] LTXD[14] LTXD[13] LTXD[12] LTXD[11] LTXD[10] LTXD[9] LTXD[8] LTXD[7] LTXD[6] LTXD[5] LTXD[4] LTXD[3] LTXD[2] LTXD[1] LTXD[0]
Type Input (SCIANY = 0)
Ball No. A5 C4 A3 D3 E4 J4 K2 M1 N4 L5 N5 N7 P8 N8 N9 P11 A6 C6 B2 C2 D1 F2 G1 G4 G3 H2 J1 P4 N1 M5 M11 N12
Function High Speed LVDS Links The low-speed receive clock (LRXC[15:0]) inputs provide timing for the receive links. Each LRXC signal is independent of the others. Each signal in LRXD[15:0] is sampled either on the rising or the falling edge of the corresponding LRXC[15:0] clock, depending the value of the LRXCINV bit of the Master Configuration register. By default, the rising edge is used. The active edge on each LRXC must only occur during those bit periods containing ATM cell data. It must be suppressed during bit periods containing transmission overhead. These inputs are only active if the SCIANY input is a logic low. Maximum clock rate is 50 MHz. The low-speed transmit data signals (LTXD[15:0]) carry the outgoing link data in bit serial format. Each LTXD signal is independent of the other signals. The most significant bit of each data byte is transmitted first. Each signal in LTXD[15:0] can be updated either on the rising or falling edge of the corresponding LTXC[15:0] clock, depending the value of the LTXCINV bit of the Master Configuration register. By default, the rising edge is used. These outputs are only active if the SCIANY input is a logic low. When SCIANY is logic high, LTXD[3] and LTXD[0] become inputs and need to be tied to VDD or VSS through a pull up or a pull down.
Output
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name LTXC[15] LTXC[14] LTXC[13] LTXC[12] LTXC[11] LTXC[10] LTXC[9] LTXC[8] LTXC[7] LTXC[6] LTXC[5] LTXC[4] LTXC[3] LTXC[2] LTXC[1] LTXC[0] IANYPHY
Type Input
Ball No.
Function High Speed LVDS Links The low-speed transmit clock (LTXC[15:0]) inputs provide timing for the transmit links. Each LTXC signal is independent of the others. Each signal in LTXD[15:0] is updated either on the rising or the falling edge of the corresponding LTXC[15:0] clock, depending on the value of the LTXCINV bit of the Master Configuration register. By default, the rising edge is used. As an option, clock gaps can be recognized to force byte alignment to the transmission overhead. These outputs are only active if the SCIANY input is a logic low. Maximum clock rate is 50 MHz.
B6 D5 (SCIANY B1 = 0) C1 E1 F1 F4 H3 H1 H4 L3 M3 N2 P7 M10 N10 Input J1
Input Parallel Bus - (SCIANY is logic high) The Input Port Any-PHY configuration (IANYPHY) input determines the protocol of the SCI-PHY/AnyPHY input port interface. IANYPHY is only active if the SCIANY input is a logic high. If IANYPHY is logic low, the interface complies to the SCI-PHY/Utopia specification. If IANYPHY is logic high, the interface complies to the Any-PHY specification. The Any-PHY protocol is supported only when the input port cell interface is configured as a bus slave (IMASTER input must be set to logic 0 if IANYPHY is high). IANYPHY is an asynchronous input and is expected to be held static.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
19
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name IMASTER
Type Input
Ball No. A6
Function High Speed LVDS Links The input port master select (IMASTER) pin determines the direction of the input port cell interface control signals. If IMASTER is low, the input port of the S/UNIDUPLEX is a bus slave and complies with the SCIPHY/Utopia or Any-PHY transmit protocol depending of the state of the IANYPHY input. The IADDR[4:0], IAVALID, IENB signals are inputs. The ICA signal is an output. If IMASTER is high, the input port of the S/UNIDUPLEX is a bus master and complies with the SCI-PHY/Utopia receive protocol (IANYPHY must be set to low if IMASTER is high). The IADDR[4:0], IAVALID, IENB signals are outputs. The ICA signal is an input. This input is only active if the SCIANY input is a logic high.
IBUS8
Input
C6
The input port bus width select (IBUS8) selects the interface bus width. When IBUS8 is high, only IDAT[7:0] are expected to present valid data and IDAT[15:8] are ignored. When IBUS8 is low, all IDAT[15:0] inputs are used. This input is only active if the SCIANY input is a logic high.
IFCLK
Input
F4
The input FIFO clock (IFCLK) is used to read words into the S/UNI-DUPLEX upstream cell buffer. IFCLK must cycle at a 52 MHz or lower instantaneous rate. All SCI-PHY/Any-PHY input port timing is relative to the rising edge of IFCLK. This input is only active if the SCIANY input is a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
20
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name ISOC
Type Input
Ball No. H2
Function High Speed LVDS Links This input is only active in SCI-PHY/Utopia bus slave or bus master modes (SCIANY = 1, ANYPHY= 0). The Input Start of Cell (ISOC) marks the start of the cell on the IDAT[15:0] bus. When ISOC is high, the first word of the cell structure is present on the IDAT[15:0] stream. It is not necessary for ISOC to be asserted for each cell, unless inband addressing is being used. An interrupt may be generated if ISOC is high during any word other than the first word of the cell structure. ISOC is sampled on the rising edge of IFCLK. If IMASTER is high, ISOC is considered valid only when the IENB signal was low in the previous cycle. If IMASTER is low, ISOC is considered valid coincident with IENB assertion.
ISX
Input
H4
The Transmit Start Of Cell (ISX) indication signal is only active in Any-PHY bus slave mode (when IANYPHY=1 and IMASTER=0). ISX marks the start of cell on the IDAT[15:0] data bus. When ISX is high, the first word of the cell structure is present on the IDAT[15:0] stream. ISX must be asserted for each cell. An interrupt may be generated if ISX is high during any word other than the expected first word of the cell structure. This input is only active if the SCIANY input is a logic high.
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21
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name IDAT[15] IDAT[14] IDAT[13] IDAT[12] IDAT[11] IDAT[10] IDAT[9] IDAT[8] IDAT[7] IDAT[6] IDAT[5] IDAT[4] IDAT[3] IDAT[2] IDAT[1] IDAT[0]
Type Input (SCIANY = 1)
Ball No. B1 C2 C1 D2 D3 D1 E1 E3 E4 F2 F1 G1 G4 H3 G3 H1
Function High Speed LVDS Links The Input Data bus (IDAT[15:0]) carries the ATM cell words that are written to the upstream cell buffer. Only IDAT[7:0] are used if the IBUS8 input is high. IDAT[15:0] is sampled on the rising edge of IFCLK. As a SCI-PHY/Utopia bus master (IMASTER=1, IANYPHY=0) the IDAT[15:0] bus is considered valid only when the IENB signal was low in the previous cycle. As a bus slave (IMASTER = 0) the IDAT[15:0] bus is considered valid when the IENB signal is asserted low or the ISX signal is asserted high. As an Any-PHY bus slave (IMASTER = 0, IANYPHY=1) IDAT[15:0] bus is not considered valid when autonomous deselection occurs after the last word of a cell. These inputs are only active if the SCIANY input is a logic high.
IPRTY
Input
B2
The Input Parity (IPRTY) signal completes the parity (programmable for odd or even parity) of the IDAT[15:0] bus when IBUS8 is low and the IDAT[7:0] bus when IBUS8 is high. A maskable interrupt and a status bit are generated upon a parity error; no other actions are taken. The IPRTY signal is sampled on the rising edge of IFCLK. As a SCI-PHY/Utopia bus master (IMASTER=1, IANYPHY=0) IPRTY is considered valid only when the IENB signal was low in the previous cycle. As a bus slave (IMASTER=0) IPRTY is considered valid coincident with IENB being asserted low or ISX being asserted high. As an Any-PHY bus slave (IMASTER = 0, IANYPHY = 1) IPRTY is not considered valid when autonomous deselection occurs after the last word of a cell. This input is only active if the SCIANY input is a logic high.
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name ICA
Type I/O
Ball No. A3
Function High Speed LVDS Links The Input Cell Available (ICA) signal provides celllevel flow control. ICA's direction depends on the state of the IMASTER input. As a SCI-PHY/Utopia bus master (IMASTER = 1, IANYPHY = 0) the S/UNI-DUPLEX polls up to 32 PHYs using the PHY address signals IADDR[4:0]. A PHY device being addressed by IADDR[4:0] is expected to indicate whether or not it has a complete cell available for transfer by driving ICA during the clock cycle following that in which it is addressed. When a cell transfer is in progress, the S/UNI-DUPLEX will not poll the PHY device which is sending the cell so PHY devices need not support the cell availability indication during cell transfer. The selection of a particular PHY device from which to transfer a cell is indicated by the state of IADDR[4:0] during the last cycle IENB is high. As a bus slave (IMASTER = 0) the S/UNI-DUPLEX indicates the ability to accept additional cells via the ICA output. When IAVALID is sampled high in SCIPHY or low in Any-PHY configuration, ICA is asserted if the cell FIFO for the logical channel addressed by IADDR[4:0] has at least one empty cell buffer. If the FIFO is full, ICA is deasserted. If a cell transfer is in progress that will fill a logical channel FIFO, ICA will also be deasserted. When IAVALID is sampled low in SCI-PHY or high in AnyPHY configuration, ICA becomes high impedance. ICA is delayed by an additional clock cycle in AnyPHY configuration. The buffer status for the particular logical channel involved is stale for a maximum of 16 cycles after the start of the cell transfer when using a 8 bit bus or 12 cycles when using a 16 bit bus. Therefore, the master should refrain from polling that logical channel in the interim.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
23
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name ICA (Cont'd)
Type
Ball No.
Function High Speed LVDS Links As a bus slave (IMASTER = 0) the S/UNI-DUPLEX can also be configured to respond to a subset of the IADDRESS[4:0] address range. In this case, ICA will remain high-impedance when the logical channel addressed by IADDR[4:0] is outside the address range specified by ICAEN[31:0] of the Input Cell Available Enable registers. ICA is sampled or updated on the rising edge of IFCLK. This signal is only active if the SCIANY input is a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
24
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name IENB
Type I/O
Ball No. B4
Function High Speed LVDS Links The active low input port enable (IENB) signal is used to initiate the reading of cells from a PHY device into the upstream cell buffer. As a SCI-PHY/Utopia bus master (IMASTER = 1, IANYPHY = 0) the S/UNI-DUPLEX asserts IENB to transfer a cell from one of up to 32 PHY devices. The source PHY is selected by the IADDR[4:0] signals. A valid word is expected on the IDAT[15:0] bus at the second rising edge of IFCLK after the enable is asserted. As a bus slave (IMASTER = 0) IENB is an input and a IDAT[15:0] word is accepted coincident with IENB being sampled low. As an Any-PHY bus slave (IMASTER = 0, IANYPHY = 1) IENB is ignored if ISX is high and may be held low upon the completion of a cell transfer, since a cell transfer is only initiated by assertion of ISX. IENB may be deasserted high at any time to pause a cell transfer.IENB is sampled or updated on the rising edge of IFCLK. The Any-PHY protocol supports autonomous deselection. As an Any-PHY slave the inputs become high impedance after the last word of a cell is transferred until the S/UNI-DUPLEX is reselected (via ISX) even if IENB is left asserted. As a SCIPHY/Utopia slave ISX is not defined, so a subsequent cell is transferred (provided one is available) if IENB is held low beyond the end of a cell. This signal is only active if the SCIANY input is a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
25
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name IADDR[4] IADDR[3] IADDR[2] IADDR[1] IADDR[0]
Type I/O
Ball No. D6 A5 D5 A4 C4
Function High Speed LVDS Links As a SCI-PHY/Utopia bus master (IMASTER = 1, IANYPHY = 0) the IADDR[4:0] signals are outputs used to address up to 32 PHY devices for the purposes of polling and selection for cell transfer. When conducting polling, in order to avoid bus contention, the S/UNI-DUPLEX inserts gap cycles during which IADDR[4:0] is set to 0x1F and IAVALID is logic 0. When this occurs, no PHY device should drive ICA during the following clock cycle. Polling is performed in incrementing sequential order. The PHY device selected for transfer is based on the IADDR[4:0] value present during the last cycle IENB was high. As a SCI-PHY/Utopia bus slave (IMASTER = 0, IANYPHY = 0) IADDR[4:0] are inputs. During polling when IAVALID is sampled high in SCI-PHY or low in Any-PHY configuration, the S/UNIDUPLEX will drive ICA with the cell buffer availability status of the logical channel indexed by IADDR[4:0] on the next IFCLK cycle. The logical channel selected for a cell transfer is determined by the IADDR[4:0] value presented when IENB was last sampled high. Cell transfer is initiated with the ISOC input being asserted. As an Any-PHY bus slave (IMASTER = 0, IANYPHY = 1) IADDR[4:0] are inputs used only for polling. Cell transfer is initiated with inband addressing (prepend Word 0 contains the address) and the ISX input. Polling occurs when IAVALID is sampled low and the S/UNI-DUPLEX drives ICA with the cell buffer availability status of the logical channel indexed by IADDR[4:0]. There is a one IFCLK cycle gap between IAVALID sampled low and ICA.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
26
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name IADDR[4] IADDR[3] IADDR[2] IADDR[1] IADDR[0] (Cont'd)
Type
Ball No.
Function High Speed LVDS Links As a bus slave device (either SCI-PHY or AnyPHY), the S/UNI-DUPLEX can be configured to be restricted to a subset of the logical channel address range. In this case, device polling or selection will occur when the logical channel addressed by IADDR[4:0] is inside the address range specified by ICAEN[31:0] of the Input Cell Available Enable registers. The IADDR[4:0] bus is updated or sampled on the rising edge of IFCLK. These signals are only active if the SCIANY input is a logic high.
IAVALID
I/O
B6
The Input Port Address Valid (IAVALID) pin indicates that the IADDR[4:0] bus is asserting a valid PHY address for polling purposes. As a SCI-PHY/Utopia bus master (IMASTER = 1, IANYPHY = 0) IAVALIV is an output. When IAVALID is deasserted, the IADDR[4:0] bus is set to 0x1F as defined by the Utopia L2 bus standard. therefore use of IAVALID is not necessary when less than 32 PHY devices are being polled. As a bus slave (IMASTER = 0) IAVALID is an input used to control the ICA output. IAVALID is active highin SCI-PHY/Utopia mode (IANYPHY = 0) and active low in Any-PHY mode (IANYPHY = 1). The ICA output is only driven when IAVALID is sampled active. If IAVALID is sampled inactive, ICA becomes high impedance. The S/UNI-DUPLEX supports polling in contiguous cycles if IAVALID is held active. ICA is delayed by an additional IFCLK cycle.IAVALID is sampled or updated on the rising edge of IFCLK. This signal is only active if the SCIANY input is a logic high. Parallel Bus - Output
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
27
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name OANYPHY
Type Input
Ball No. M5
Function High Speed LVDS Links The Output Port Any-PHY configuration (OANYPHY) input determines the protocol of the SCI-PHY/Any-PHY output port interface. OANYPHY is only active if the SCIANY input is a logic high. If OANYPHY is logic low, the interface complies to the SCI-PHY/Utopia specification. If OANYPHY is logic high, the interface complies to the Any-PHY specification. The Any-PHY protocol is supported only when the output port cell interface is configured as a bus slave (IMASTER input must be set to logic low if OANYPHY is high). OANYPHY is an asynchronous input and is expected to be held static.
OMASTER
Input
M11
The Output Port Master select (OMASTER) pin determines the direction of the output port cell interface control signals. If OMASTER is high the OANYPHY must be low. The output port of the S/UNI-DUPLEX is a bus master that complies with the SCI-PHY/Utopia transmit protocol. The OADDR[4:0], OAVALID, OENB signals are outputs and the OCA signal is an input. If OMASTER is low, the output port of the S/UNIDUPLEX is a bus slave and complies with the SCIPHY/Utopia or the Any-PHY receive protocol depending on the state of the OANYPHY input. The OADDR[4:0], OAVALID, OENB signals are inputs. The OCA signal is an output. This input is only active if the SCIANY input is a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
28
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name OBUS8
Type Input
Ball No. P4
Function High Speed LVDS Links The output port bus width select (OBUS8) selects the output port interface bus width. When OBUS8 is high, only ODAT[7:0] present valid data and ODAT[15:8] are held low. When OBUS8 is low, all ODAT[15:0] outputs are used. This input is only active if the SCIANY input is a logic high.
OFCLK
Input
N5
The output port FIFO clock (OFCLK) is used to transfer cells from the internal downstream cell buffer to the PHY devices. OFCLK must cycle at a 52 MHz or lower instantaneous rate, but a high enough rate to avoid a FIFO overflow. All SCIPHY/Any-PHY output port timing is relative to the rising edge of OFCLK. This input is only active if the SCIANY input is a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
29
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name OSOC
Type Output
Ball No. L7
Function High Speed LVDS Links In all bus modes, OSOC is updated on the rising edge of OFCLK. When not presenting valid data, OSOC is high impedance. In SCI-PHY/Utopia bus slave mode (OMASTER = 0, OANYPHY = 0) the output port start of cell (OSOC) indication signal marks the first word of the cell transfer on the ODAT[15:0] data bus. OSOC is driven immediately upon sampling OENB low if the previous polling cycle resulted in this device being selected (see the OCA description below). In Any-PHY bus slave mode (OMASTER = 0, OANYPHY = 1) the output port start of cell (OSOC) indication signal marks the second word of the cell transfer on the ODAT[15:0] data bus. OSOC is driven after one OFCLK cycle delay upon sampling OENB low if the previous polling cycle resulted in this device being selected (see the OCA description below). Autonomous deselection occurs after the last word of a cell resulting in setting OSOC highimpedance until reselection. In SCI-PHY/Utopia bus master mode (OMASTER = 1, OANYPHY = 0) the output port start of cell (OSOC) indication signal marks the first word of the cell transfer on the ODAT[15:0] data bus. OSOC is valid coincident with OENB assertion.. When OANYPHY is high, autonomous deselection occurs after the last word of a cell resulting in setting OSOC high-impedance until reselection. This output is only active if the SCIANY input is a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
30
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name OSX
Type Output
Ball No. P8
Function High Speed LVDS Links The Output Start of Transfer (OSX) is only active in Any-PHY bus slave mode (OANYPHY = 1 OMASTER = 0). When OANYPHY is logic low, OSX is held low during cell transfer or highimpedance otherwise. OSX marks the start of the cell on the ODAT[15:0] bus. When OSX is high, the first word of the cell structure is present on the ODAT[15:0] stream. OSX is updated on the rising edge of OFCLK and considered valid only when the OENB signal was sampled low in the previous cycle and the S/UNIVORTEX device was selected after the polling process. OSX becomes high impedance (with a cycle latency) upon sampling OENB high or if the S/UNI-VORTEX device is not selected for transfer. When OANYPHY is high, autonomous deselection occurs after the last word of a cell resulting in setting OSX high-impedance until reselection. This input is only active if the SCIANY input is a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
31
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name ODAT[15] ODAT[14] ODAT[13] ODAT[12] ODAT[11] ODAT[10] ODAT[9] ODAT[8] ODAT[7] ODAT[6] ODAT[5] ODAT[4] ODAT[3] ODAT[2] ODAT[1] ODAT[0]
Type Output (SCIANY = 1)
Ball No. J4 K3 K2 L3 L2 M1 M3 N2 P2 N4 M4 L5 N6 L6 N7 P7
Function High Speed LVDS Links The output port cell data bus (ODAT[15:0]) carries the ATM cell octets that are transferred to the PHY devices. Only ODAT[7:0] are used if OBUS8 is high. The ODAT[15:0] bus is updated on the rising edge of OFCLK. As a SCI-PHY/Utopia bus master (OMASTER = 1, OANYPHY = 0), the ODAT[15:0] bus is considered valid coincident with OENB assertion. As a bus slave (OMASTER = 0), the ODAT[15:0] bus is considered valid only when the S/UNIVORTEX device was selected after the polling process and the OENB signal is sampled low. As an SCI-PHY/Utopia bus slave (OMASTER = 0, OANYPHY = 0) ODAT[15:0] is driven immediately upon sampling OENB low it has an additional OFCLK cycle latency. When not presenting valid data, the ODAT[15:0] bus is high impedance. Autonomous deselection occurs after the last word of a cell resulting in setting ODAT[15:0] highimpedance until reselection. These outputs are only active if the SCIANY input is a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
32
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name OPRTY
Type Output
Ball No. J2
Function High Speed LVDS Links The output port parity (OPRTY) signal completes the parity (programmable for odd or even parity) of the ODAT[15:0] bus when OBUS8 is low and the ODAT[7:0] bus when OBUS8 is high. The OPRTY signal is updated on the rising edge of OFCLK. As a SCI-PHY/Utopia bus master (OMASTER = 1, OANYPHY = 0) OPRTY is considered valid coincident with OENB assertion. As a bus slave (OMASTER = 0) the OPRTY bus is considered valid only when the S/UNI-VORTEX device was selected after the polling process and the OENB signal is sampled low. As an SCIPHY/Utopia bus slave (OMASTER = 0, OANYPHY = 0) OPRTY is driven immediately upon sampling OENB low, but as an Any-PHY bus slave (OMASTER = 0, OANYPHY = 1) it has an additional cycle latency when OANYPHY is logic high. When not presenting valid data, OPRTY is high impedance. As an Any-PHY bus slave autonomous deselection occurs after the last word of a cell resulting in setting OPRTY high-impedance until reselection. This output is only active if the SCIANY input is a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
33
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name OCA
Type I/O
Ball No. N8
Function High Speed LVDS Links The Output Cell Available (OCA) signal provides cell-level flow control. OCA's direction depends on the state of the OMASTER input. As a SCI-PHY/Utopia bus master (OMASTER = 1, OANYPHY = 0) the S/UNI-DUPLEX polls up to 32 PHYs using the PHY address signals OADDR[4:0]. A PHY device being addressed by OADDR[4:0] is expected to indicate whether or not it can accept a cell by driving the OCA during the clock cycle following that in which it is addressed. When a cell transfer is in progress, the S/UNI-DUPLEX will not poll the PHY device which is receiving the cell so PHY devices need not support the cell availability indication during cell transfer. The selection of a particular PHY device to which a cell will be written is indicated by the state of OADDR[4:0] during the last cycle OENB was high. As a bus slave (OMASTER = 0) the S/UNIDUPLEX indicates the existence of at least one complete cell within its buffers when polled. The S/UNI-DUPLEX round-robins between the logical channel cell FIFOs to autonomously select cells, so the interface appears as a single PHY slave. When OAVALID is sampled high in SCI-PHY or low in Any-PHY configuration and the sampled OADDR[4:0] matches the OAD[4:0] bits in the Output Address Match register, OCA is asserted if at least one cell is available for transfer. If all logical channel FIFOs are empty, OCA is deasserted. If a cell transfer is in progress that will read the last available cell, OCA will also be deasserted. When OAVALID is sampled low, OCA becomes high impedance. OCA is delayed by an additional clock cycle in Any-PHY configuration. OCA is sampled or updated on the rising edge of OFCLK. This signal is only active if the SCIANY input is a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
34
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name OENB
Type I/O
Ball No. P9
Function High Speed LVDS Links The active low output port enable (OENB) signal is used to enact cell transfers from the output port. OENB's direction depends on the state of the OMASTER input. As a SCI-PHY/Utopia bus master (OMASTER = 1, OANYPHY = 0) OENB is an output and a valid word is output on the ODAT[15:0] bus coincidentally with the assertion of OENB. The state of OADDR[4:0] during the last cycle OENB was high selects the PHY to which the cell is destined. Once asserted low, OENB will remain low until the cell transfer is complete. As a bus slave (OMASTER = 0) OENB is an input. When OENB is sampled low and the S/UNIDUPLEX has been selected, a word is output on bus ODAT[15:0]. Selection occurs when OENB is last sampled high if the OADDR[4:0] value equals the state of the OAD[4:0] bits in the Output Address Match register and OAVALID is sampled is its asserted state. OENB must be low for the duration of the cell transfer. As a SCI-PHY/Utopia slave valid data is driven immediately upon sampling OENB low. As a Any-PHY slave the OSX, OSOP, ODAT[15:0] and OPRTY outputs have an additional cycle of latency. It is permissible to pause a cell transfer by deasserting OENB high. As a SCI-PHY/Utopia slave the S/UNI-DUPLEX's must be reselected before the cell transfer can resume. As a Any-PHY slave the cell transfer resumes unconditionally when OENB is asserted low again. In either case, a cell transfer must be completed before another device on the bus is selected.
The Any-PHY protocol supports autonomous deselection. As an Any-PHY slave the outputs become high impedance after the last word of a cell is transferred until the S/UNI-DUPLEX is reselected (via OSX) even if OENB is left asserted. As a SCIPHY/Utopia slave OSX is not defined, so a subsequent cell is transferred (provided one is available) if OENB is held low beyond the end of a cell. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 35
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name OENB
Type I/O
Ball No.
Function High Speed LVDS Links (Continued) When OENB is sampled high or the S/UNIDUPLEX is not selected, no read is performed and outputs ODAT[15:0], OPRTY, OSX and OSOC become high impedance. OENB is sampled or updated on the rising edge of OFCLK. This signal is only active if the SCIANY input is a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
36
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name OADDR[4] OADDR[3] OADDR[2] OADDR[1] OADDR[0]
Type I/O
Ball No. N9 M10 N10 L10 P11
Function High Speed LVDS Links As a SCI-PHY/Utopia bus master (OMASTER = 1, 0ANYPHY = 0) the OADDR[4:0] signals are used to address up to 32 PHY devices for the purposes of polling and selection for cell transfer. When conducting polling, in order to avoid bus contention, the S/UNI-DUPLEX inserts gap cycles during which the OADDR[4:0] bus is set to 0x1F and OAVALID is logic 0. When this occurs, no PHY device should drive OCA during the following clock cycle. The polling order is based on the existence of cells in the downstream cell buffer. The PHY device selected for transfer is based on the OADDR[4:0] value present during the last cycle OENB is high. As a bus slave the OADDR[4:0] signals are inputs. When OAVALID is sampled high in SCI-PHY/Utopia or low in Any-PHY configuration and the sampled OADDR[4:0] matches the OAD[4:0] bits in the Output Address Match register, OCA is asserted if at least one cell is available for transfer. OCA is delayed by an additional OFCLK cycle in Any-PHY configuration. If the OADDR[4:0] value equals the state of the OAD[4:0] bits in the Output Address Match register when the OENB is last sampled high, the S/UNI-DUPLEX will initiate a cell transfer. As a SCI-PHY/Utopia bus slave (OMASTER = 0, OANYPHY = 0) the device must be reselected to resume a cell transferred that has been halted by deasserting OENB high. The OADDR[4:0] bus is sampled or updated on the rising edge of OFCLK. These signals are only active if the SCIANY input is a logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
37
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name OAVALID
Type I/O
Ball No. M9
Function High Speed LVDS Links The Output Address Valid (OAVALID) pin indicates that the OADDR[4:0] bus is asserting a valid PHY address for polling purposes. As a SCI-PHY/Utopia bus master (OMASTER = 1, OANYPHY = 0) OAVALID is an output. When this signal is deasserted, the OADDR[4:0] bus is also set to 0x1Fas defined by the Utopia L2 bus standard. Therefore. Use of OAVALID is not necessary when less than 32 PHY devices are being polled. As a bus slave (OMASTER = 0) OAVALID is an input used to control the OCA output. The OCA output is only driven when OAVALID is asserted (sampled high in SCI-PHY/Utopia or sample low in Any-PHY configuration) and the sampled OADDR[4:0] value matches the OAD[4:0] bits in the Output Address Match register. If OAVALID is deasserted (sampled low in SCI-PHY/Utopia) or high in Any-PHY configuration) OCA becomes high impedance. The S/UNI-DUPLEX supports polling in contiguous cycles if OAVALID is held high. OCA is delayed by an additional OFCLK cycle in Any-PHY bus configuration. OAVALID is sampled or updated on the rising edge of OFCLK. This signal is only active if the SCIANY input is a logic high. Microprocessor Bus
CSB
Input
D8
The active-low chip select (CSB) signal is low during S/UNI-DUPLEX register accesses. Note that when not being used, CSB must be tied high. If CSB is not required (i.e., registers accesses are controlled using the RDB and WRB signals only), CSB must be connected to an inverted version of the RSTB input.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
38
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name RDB
Type Input
Ball No. A8
Function High Speed LVDS Links The active-low read enable (RDB) signal is low during S/UNI-DUPLEX register read accesses. The S/UNI-DUPLEX drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. The active-low write strobe (WRB) signal is low during S/UNI-DUPLEX register write accesses. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low. The bi-directional data bus D[7:0] is used during S/UNI-DUPLEX register read and write accesses.
WRB
Input
D9
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[7]/TRS A[6] A[5] A[4] A[3] A[2] A[1] A[0] RSTB
I/O
C14 D13 D12 D14 F11 F13 F12 F14 C9 A9 B9 B10 D11 A11 C11 B11 A10
Input
The address bus A[7:0] selects specific registers during S/UNI-DUPLEX register accesses. The test register select (TRS) signal selects between normal and test mode register accesses. TRS is high during test mode register accesses, and is low during normal mode register accesses. The active-low reset (RSTB) signal provides an asynchronous S/UNI-DUPLEX reset. RSTB is a Schmitt triggered input with an integral pull-up resistor. The address latch enable (ALE) is active-high and latches the address bus A[5:0] when low. When ALE is high, the internal address latches are transparent. It allows the S/UNI-DUPLEX to interface to a multiplexed address/data bus. ALE has an integral pull-up resistor.
Input
ALE
Input
B8
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
39
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name INTB
Type OD Output
Ball No. B7
Function High Speed LVDS Links
RSTOB
OD Output
The active-low interrupt (INTB) signal goes low when a S/UNI-DUPLEX interrupt source is active and that source is unmasked. The S/UNI-DUPLEX may be enabled to report many alarms or events via interrupts. INTB is tristated when the interrupt is acknowledged via an appropriate register access. INTB is an open drain output. A2 The active low Reset Output pin may be used to reset other devices. RSTOB is asserted low when RSTB is low, the RESETO bit of the Master Configuration register is set or if a "remote reset activate" bit oriented code has been validated for the active link. The "remote reset deactivate" code sets RSTOB to high impedance unless the RESETO bit is set. JTAG Boundary Scan Port B13 The test clock (TCK) signal provides timing for test operations that are carried out using the IEEE P1149.1 test access port. The test mode select (TMS) signal controls the test operations that are carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull-up resistor. The test data input (TDI) signal carries test data into the S/UNI-DUPLEX via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull-up resistor. The test data output (TDO) signal carries test data out of the S/UNI-DUPLEX via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output which is inactive except when scanning of data is in progress.
TCK
Input
TMS
Input
B12
TDI
Input
A12
TDO
Tristate
P13
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Ball Name TRSTB
Type Input
Ball No. A13
Function High Speed LVDS Links The active-low test reset (TRSTB) signal provides an asynchronous S/UNI-DUPLEX test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull-up resistor. Note that when not being used, TRSTB must be connected to the RSTB input. Power and Ground
BIAS
Power
A7
When tied to +5V, the BIAS input is used to bias the wells in the input and I/O pads so that the pads can tolerate 5V on their inputs without forward biasing internal ESD protection devices. When tied to +3.3V, the inputs and bi-directional inputs will only tolerate 3.3V level inputs. The digital power (VDD) pins should be connected to a well-decoupled +3.3 V DC supply.
VDD
Power
B3 C5 C13 D10 E2 E14 F3 K1 L1 L4 L9 M7 M12 N3 N13 P6
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Ball Name VSS
Type Ground
Ball No. B5 C3 C8 C10 C12 D4 D7 E12 G2 J3 K4 L8 M2 M6 M8 N11 N14 P3 P5 P10 M13
Function High Speed LVDS Links The digital ground (VSS) pins should be connected to GND.
QAVD
Analog Power
Quiet Analog Power (QAVD). QAVD should be connected to analog +3.3 V. It should be electrically isolated (as much as possible) from the other power connections. Quiet Analog Ground (QAVS). QAVS should be connected to analog GND. It should be electrically isolated (as much as possible) from the other ground connections. The power (CAVD) pin for the analog clock synthesis unit. This pin should be connected to analog +3.3V. It should be electrically isolated (as much as possible) from the other power connections. The ground (CAVS) pin for the analog clock synthesis unit. This pin should be connected to analog GND. It should be electrically isolated (as much as possible) from the other ground connections.
QAVS
Analog Ground
M14
CAVD
Analog Power
L11
CAVS
Analog Ground
L12
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DUAL SERIAL LINK PHY MULTIPLEXER
Ball Name RAVD
Type Analog Power
Ball No. J11
Function High Speed LVDS Links The power (RAVD) pin for the LVDS receivers. This pin should be connected to analog +3.3V. It should be electrically isolated (as much as possible) from the other power connections. The ground (RAVS) pin for the LVDS receivers. This pin should be connected to analog GND. It should be electrically isolated (as much as possible) from the other ground connections. The power (TAVD) pins for the LVDS transmitters. These pins should be connected to analog +3.3V. These should be electrically isolated (as much as possible) from the other power connections. The ground (TAVS) pins for the LVDS transmitters. These pins should be connected to analog GND. These should be electrically isolated (as much as possible) from the other ground connections. The Thermal Vias (GND) are used to improve thermal conductance of the device package. They should be connected to the PCB ground plane. The GND pins are not electrically connected to the other ground pins of the package.
RAVS
Analog Ground
J12
TAVD
Analog Power
G11 K11
TAVS
Analog Ground
H12 K12
GND
Thermal Vias
G7 G8 H7 H8
Notes on Pin Description: 1. All S/UNI-DUPLEX inputs and bi-directionals present minimum capacitive loading and operate at TTL logic levels, except RXD1+/- and RXD2+/-. 2. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors. 3. The recommended power supply sequencing is as follows: 1. 3.1 During power-up, the voltage on the BIAS pin must be kept equal to or greater than the voltage on the VDD pins, to avoid damage to the device. 2. 3.2 The VDD power must be applied before input pins are driven or the input current per pin be limited to less than the maximum DC input current specification (20 mA).
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3. 3.3 Analog power supplies (QAVD, CAVD, RAVD, TAVD) must be applied after VDD have been applied or they must be current limited to the maximum latch-up current specification (100 mA). In operation, the differential voltage measured between AVD supplies and VDD must be less than 0.5 V. The relative power sequencing of the multiple AVD power supplies is not important. 4. 3.4 Power down the device in the reverse sequence.
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9
FUNCTIONAL DESCRIPTION The S/UNI-DUPLEX supports two distinct methods of interconnection to modems, PHYs and other ATM devices: via a parallel bus interface or via 16 clocked serial data interface. In either case the primary function of the S/UNIDUPLEX is to transfer cells between the external devices and the high speed LVDS serial links. At far end of the LVDS link another S/UNI-DUPLEX device or a S/UNI-VORTEX device must be connected. See the PMC-Sierra Data Sheet for the PM7351 S/UNI-VORTEX for details on that device. In the LVDS transmit direction, cells are read from the external devices and multiplexed onto the LVDS link. Flow control, alarm, PHY identification, and other control information is added to each cell to ensure a managed link is maintained. In the LVDS receive direction, system overhead is stripped off each cell before it is sent to the appropriate device on the parallel bus or over the clocked serial data interfaces. In bus slave mode, the PHY ID is left in the cell, typically for use by an ATM layer device such as PMC-Sierra's S/UNI-ATLAS so that the cell source can be determined. In bus master mode, or in clocked serial interface mode the PHY ID is stripped off and used to direct the cell to the appropriate Utopia slave device or to the appropriate clocked serial interface. For a discussion of overall system architecture issues, the reader is referred to a companion document provided by PMC-Sierra titled S/UNI-VORTEX & S/UNIDUPLEX TECHNICAL OVERVIEW. The document number is PMC-981025 and it can be obtained by one of the various means described on the last page of this document. The remainder of this section focuses on the interfaces and functionality of a single S/UNI-DUPLEX device, although the reader should also view things in the context of the attached far-end device (either a S/UNI-DUPLEX or a S/UNIVORTEX).
9.1
Parallel Bus Interface The S/UNI-DUPLEX's parallel interface. is selected when the SCIANY input is tied high. This interface supports three types of bus: Utopia Level 2, SCI-PHY Level 2, and Any-PHY. Table 1 provides the correspondence between the S/UNI-DUPLEX pin names and the Utopia Level 2, SCI-PHY Level 2 and Any-PHY signals. The Any-PHY bus format is enabled when the IANYPHY and OANYPHY inputs are tied high, SCI-PHY or Utopia is selected when the inputs are tied low. Input and output
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bus formats need not be the same. When configured as a SCI-PHY or Utopia Level 2 interface the S/UNI-DUPLEX can be either a bus master or bus slave, as determined by the IMASTER and OMASTER inputs. When configured as an Any-PHY interface, the S/UNI-DUPLEX can only be a bus slave. 8 and 16 bit wide interfaces are supported in all configurations, and are determined by the IBUS8 and OBUS8 inputs. Table 1 Signal Name Cross-Reference
S/UNIDUPLEX PIN Name
IFCLK
IENB IADDR[4:0] IAVALID IDAT[15:0] IPRTY ICA ISOC ISX OFCLK OENB OADDR[4:0] OAVALID ODAT[15:0] OPRTY OCA OSOC OSX
UTOPIA Level 2 Bus Slave
TxClk
TxEnb* TxAddr[4:0] n/a TxData[15:0] TxPrty TxClav TxSOC n/a RxClk RxEnb* RxAddr[4:0] n/a RxData[15:0] RxPrty RxClav RxSOC n/a
UTOPIA Level 2 Bus Master
RxClk
RxEnb* RxAddr[4:0] n/a RxData[15:0] RxPrty RxClav RxSOC n/a TxClk TxEnb* TxAddr[4:0] n/a TxData[15:0] TxPrty TxClav TxSOC n/a
SCI-PHY Level 2 Bus Slave
TFCLK
TWRENB TADDR[4:0] TAVALID TDAT[15:0] TPRTY TCA TSOC n/a RFCLK RWRENB RADDR[4:0] RAVALID RDAT[15:0] RPRTY RCA RSOC n/a
SCI-PHY Any-PHY Bus Level 2 Slave Bus Master
RFCLK
RWRENB RADDR[4:0] RAVALID RDAT[15:0] RPRTY RCA RSOC n/a TFCLK TWRENB TADDR[4:0] TAVALID TDAT[15:0] TPRTY TCA TSOC n/a
TCLK
TENB TADR[4:0] TADR[5] TDAT[15:0] TPRTY TPA TSOP TSX RCLK RENB RADR[4:0] RADR[5] RDAT[15:0] RPRTY RPA RSOP RSX
Utopia and SCI-PHY are electrically compatible, the only difference is that Utopia does not support the use of the optional OAVALID and IAVALID pins. Therefore, whether the input and output buses are Utopia or SCI-PHY is determined by the inclusion or exclusion of optional words in the cell format that is transferred across the bus. The cell formats supported are presented in Fig. 6 and Fig. 7. As programmed through register bits, bytes may be prepended to a basic ATM cell to support applications where user defined context information is carried inband. Also, inclusion of the H5 and H5/UDF fields (8 bit and 16 bit modes respectively) is optional under most configurations. For bus slave configurations, the PHY
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identifier and an inband address can be included in an additional prepend word or in the H5/UDF fields, as discussed below. By default, none of the optional words are prepended, and the H5 or H5/UDF field is included. Be aware that cells are transported transparently across the LVDS links. There are no constraints on the contents. Therefore, data streams other than ATM cells can be transferred across the parallel bus interface interface; only the bus timing and bus protocols need be respected. It is also important to note that the treatment of the H5/UDF field, the address prepend (Word 0), and the optional User Prepend on the input and output buses are independent from how their corresponding fields on the LVDS link are configured. See Section 12.2 for further details. 9.1.1 SCI-PHY or Utopia Bus Master The SCI-PHY/Utopia bus master format is enabled when the IANYPHY and OANYPHY inputs are tied low and the IMASTER and OMASTER inputs are tied high. The SCI-PHY/Utopia bus master interface supports up to 32 PHY entities provided the IAVALID and OAVALID signals are used; otherwise, 31 are supported. The interface is fully Utopia Level 2 compliant when IAVALID and OAVALID are not used. It is assumed the PHY devices perform all Transmission Convergence (TC) functions including cell delineation, cell rate decoupling, payload scrambling, HCS insertion and cell filtering upon header errors. In the ingress direction (cells are transferred from the input bus to the LVDS link), the S/UNI-DUPLEX uses round robin polling to provide equal access to all PHY devices. As directed by flow control information on the LVDS link (and optionally through S/UNI-DUPLEX configuration), any PHY device may temporarily be removed from the polling sequence. Data transfers are cell based, that is, an entire cell is transferred from one PHY device before another is selected. Polling occurs concurrently with cell transfers to ensure maximum throughput. The SCI-PHY/Any-PHY Input Configuration 1 register (0x0C) determines the cell format of the input bus. Unlike the Any-PHY bus mode, a SCI-PHY/Utopia bus master does not require and hence does not support embedded PHY ID. The cell length options for the 8 bit bus (shown in Fig. 6) are described in Table 2. 16 bit bus options (shown in Fig. 7) are described in Table 3.
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Table 2 Eight Bit SCI-PHY/Utopia Bus Master, Input Configuration
Byte
# bytes 52 53 53 54 54 55
0 N N N N N N
1 N N Y Y Y Y
2 N N N N Y Y
7 N Y N Y N Y
Register 0x0C H5UDF PRELEN
Notes
Short cell, no H5 byte Default, Utopia compatible 1 user byte then H1-H4 1 user byte then H1-H5 2 user bytes then H1-H4. 2 user bytes then H1-H5.
0 1 0 1 0 1
00 00 01 01 10 10
Table 3 Sixteen Bit SCI-PHY/Utopia Bus Master, Input Configuration
Word
# bytes 52 54 54 56
0 N N N N
1 N N Y Y
4 N Y N Y
Register 0x0C H5UDF PRELEN
Notes
Short cell, no H5/UDF field Default, Utopia compatible 1 user word then H1-H4 1 user word, H1-H4, then H5/UDF
0 1 0 1
00 00 01 01
In the egress direction (cells are transferred from the LVDS link to the output bus.), only those PHY devices are polled for which there is a cell in the internal cell buffer. The cell buffer is organized as 32 FIFOs, each associated with a single PHY device. This arrangement prevents head-of-line blocking. As per the ingress interface, transfers are cell based and polling is concurrent with cell transfers. The SCI-PHY/Any-PHY Output Configuration register (0x14) determines the cell format of the output bus. A SCI-PHY/Utopia bus master neither requires nor supports embedded PHY ID. The cell length options for the 8 bit bus (shown in Fig. 6) are described in Table 4. 16 bit bus options (shown in Fig. 7) are described in Table 5.
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Table 4 Eight Bit SCI-PHY/Utopia Bus Master, Output Configuration
Byte
# bytes 52 53 53 54 54 55
0 N N N N N N
1 N N Y Y Y Y
2 N N N N Y Y
7 N Y N Y N Y
Register 0x14 INADD H5 PRE UDF UDF LEN
Notes
Short cell, no PHY ID is generated Default setting. Utopia compatible, standard 53 byte cell, no PHY ID 1 user byte, H1-H4, no PHY ID 1 user byte, H1-H5, no PHY ID 2 user bytes, H1-H4, no PHY ID 2 user bytes, H1-H5, no PHY ID
X X X X X X
0 1 0 1 0 1
00 00 01 01 10 10
Table 5 Sixteen Bit SCI-PHY/Utopia Bus Master, Output Configuration
Word
# bytes 52 54 54 56
0 N N N N
1 N N Y Y
4 N Y N Y
Register 0x14 INADD H5 PRE UDF UDF LEN
Notes
Short cell, no PHY ID Default, Utopia compatible, no PHY ID 2 user bytes, H1-H4, no PHY ID 2 user bytes, H1-H4, H5/UDF, no PHY ID
X X X X
0 1 0 1
00 00 01 01
9.1.2 SCI-PHY or Utopia Bus Slave The SCI-PHY/Utopia bus slave format is enabled when the IANYPHY, OANYPHY, IMASTER, and OMASTER inputs are all tied low. In the ingress direction (cells are transferred from the parallel bus input port to the LVDS links), the port presents itself as 32 PHY entities but is fully Utopia Level 2 compatible when 31 or fewer PHYs are active and IAVALID is tied high. Cells read from the bus are queued in a dedicated FIFO for each virtual PHY (hereafter referred to as a logical channel). The ability of the FIFOs to accept additional cells is discovered through polling using the IADDR[4:0] and IAVALID inputs. Upon IAVALID being sampled high the ICA output is asserted if the cell FIFO for the logical channel addressed by IADDR[4:0] has at least one empty cell buffer. If the FIFO is full, ICA is deasserted. If a cell transfer is in progress that will fill a logical channel FIFO, ICA will also be deasserted. If IAVALID is sampled low (in SCI-PHY mode) ICA becomes high impedance. When operating as a SCI-PHY/Utopia interface, a cell transfer is effected by the assertion low of IENB. The logical channel FIFO to which the cell is written is selected by the IADDR[4:0] value sampled when IENB was last sampled high.
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The SCI-PHY/Any-PHY Input Configuration 1 register (0x0C) determines the cell format of the input bus. A SCI-PHY/Utopia input bus slave neither requires nor supports embedded PHY ID. The cell length options for the 8 bit bus (shown in Fig. 6) are described in Table 6. 16 bit bus options (shown in Fig. 7) are described in Table 7. Note that these options are identical to the SCIPHY/Utopia input bus master configuration. Table 6 Eight Bit SCI-PHY/Utopia Bus Slave, Input Configuration
Byte
# bytes 52 53 53 54 54 55
0 N N N N N N
1 N N Y Y Y Y
2 N N N N Y Y
7 N Y N Y N Y
Register 0x0C H5UDF PRELEN
Notes
H1-H4, no H5 byte Default, Utopia compatible 1 user byte then H1-H4 1 user byte then H1-H5 2 user bytes then H1-H4 2 user bytes then H1-H5
0 1 0 1 0 1
00 00 01 01 10 10
Table 7 Sixteen Bit SCI-PHY/Utopia Bus Slave, Input Configuration
Word
# bytes 52 54 54 56
0 N N N N
1 N N Y Y
4 N Y N Y
Register 0x0C H5UDF PRELEN
Notes
H1-H4, no H5/UDF field Default, Utopia compatible 1 user word then H1-H4 1 user word, H1-H4, then H5/UDF
0 1 0 1
00 00 01 01
In the egress direction (cells are transferred from the LVDS to the output port), the port appears as a single addressable SCI-PHY/Utopia Level 2 slave. The cells received on the high-speed serial link are queued in FIFOs dedicated to each logical channel. The corresponding PHY ID of each cell is encoded in system prepend bytes sent over the LVDS link. The S/UNI-DUPLEX autonomously multiplexes the traffic from up to 32 logical channels and presents it as a single cell stream on the output bus. If at least one cell is present in any of the FIFOs, OCA will drive high when the device is polled. Polling occurs when OAVALID is sampled high and the sampled OADDR[4:0] matches the OAD[4:0] bits in the Output Address Match register. Utopia L2 compatibility is achieved if OAVALID is tied high and OAD[4:0] is not all ones.
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A cell transfer will be enacted if the OADDR[4:0] value equals the state of the OAD[4:0] bits in the Output Address Match register when the OENB is last sampled high. In SCI-PHY bus mode a word is prepended to the transferred ATM cell to identify the cell's source (i.e. a logical channel number). To retain Utopia Level 2 compatibility, the word identifying the logical channel can be placed in the H5/UDF field. The three most significant bits of the channel number in the 8-bit format and the 11 most significant bits of the prepend in the 16-bit format are derived from the contents of the Extended Address Match registers, which default to all zeros. The SCI-PHY/Any-PHY Output Configuration register (0x14) determines the cell format on the output bus. The cell length options for the 8 bit bus (shown in Fig. 6) are described in Table 8. 16 bit bus options (shown in Fig. 7) are described in Table 9. Table 8 Eight Bit SCI-PHY/Utopia Bus Slave, Output Configuration
Byte
# bytes 52 53 53 54 54 55 53
0 N N N N N N N
1 N N Y Y Y Y N
2 N N N N Y Y N
7 N Y N Y N Y Y
Register 0x14 INADD H5 PRE UDF UDF LEN
Notes
H1-H4 only, no PHY ID is generated Default setting. Utopia compatible, standard 53 byte cell, no PHY ID 1 user byte, H1-H4, no PHY ID 1 user byte, H1-H5, no PHY ID 2 user bytes, H1-H4, no PHY ID 2 user bytes, H1-H5, no PHY ID Most common setting when Utopia compatibility is desired. Standard 53 byte cell, PHY ID embedded in H5. 1 user byte, H1-H4, PHY ID in H5 2 user bytes, H1-H4, PHY ID in H5
0 0 0 0 0 0 1
0 1 0 1 0 1 X
00 00 01 01 10 10 00
54 55
N N
Y Y
N Y
Y Y
1 1
X X
01 10
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Table 9 Sixteen Bit SCI-PHY/Utopia Bus Slave, Output Configuration
Word
# bytes 52 54 54 56 54 56
0 N N N N N N
1 N N Y Y N Y
4 N Y N Y Y Y
Register 0x14 INADD H5 PRE UDF UDF LEN
Notes
H1-H4 only, no PHY ID Default, Utopia compatible, no PHY ID 2 user bytes, H1-H4, no PHY ID 2 user bytes, H1-H4, H5/UDF, no PHY ID Most common setting when Utopia compatibility is desired. Standard 54 byte cell, PHY ID embedded in H5/UDF. 2 user bytes, H1-H4, PHY ID in H5/UDF
0 0 0 0 1 1
0 1 0 1 X X
00 00 01 01 00 01
9.1.3 Any-PHY Slave The Any-PHY bus slave format is enabled when the IANYPHY and OANYPHY inputs are high, and IMASTER, and OMASTER inputs are all tied low. In the ingress direction (cells are transferred from the parallel bus input port to the LVDS links), the port presents itself as 32 PHY entities. Cells read from the bus are queued in a dedicated FIFO for each logical channel. As in the SCI-PHY bus mode, the ability of the FIFOs to accept additional cells is discovered through polling using the IADDR[4:0] and IAVALID inputs. Upon IAVALID being sampled low (note this is opposite to SCI-PHY mode) the ICA output is asserted if the cell FIFO for the logical channel addressed by IADDR[4:0] has at least one empty cell buffer. If the FIFO is full, ICA is deasserted. If a cell transfer is in progress that will fill a logical channel FIFO, ICA will also be deasserted. If IAVALID is sampled high ICA becomes high impedance. ICA is delayed by one bus cycle (i.e. one IFCLK cycle) in the Any-PHY bus configuration. In Any-PHY mode cell transfer is initiated using inband selection. The first word of the cell, coincident with the assertion of the ISX signal, is used for logical channel selection. Cells are accepted by the S/UNI-DUPLEX if the value in the Extended Address field of Word 0 agrees with the Extended Address Match registers over the range of bits specified by the Extended Address Mask registers. Table 10 summarizes the distinctions between the SCI-PHY/Utopia and Any-PHY protocols in the ingress direction.
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Table 10 SCI-PHY/Utopia and Any-PHY Comparison, Ingress Direction
Attribute Latency SCI-PHY ICA is driven high or low immediately upon sampling IAVALID high and becomes high impedance immediately upon sampling IAVALID low. Logical channel is selected by IADDR[4:0] when IENB was last sampled high. Unused. High coincident with the first word of the cell data structure. Not supported. A subsequent cell is input (provided space is available) if IENB is held low beyond the end of a cell. Any-PHY ICA is driven or becomes high impedance on the IFCLK rising edge following the one that samples a IAVALID low or high respectively. An extra word (Word 0) is prepended to the cell coincident with the assertion of the ISX signal. Word 0 is used for logical channel selection High coincident with the first word of the cell data structure. Unused in the S/UNI-DUPLEX. Supported. Subsequent writes are ignored if IENB is held low until ISX input is asserted.
Logical Channel Selection ISX ISOC Autonomous deselection
The SCI-PHY/Any-PHY Input Configuration 1 register (0x0C) determines the cell format of the input bus. An Any-PHY input bus slave requires the embedded PHY ID to be present in Byte 0 or Word 0. The cell format options for the 8 bit bus (shown in Fig. 6) are described in Table 11. 16 bit bus options (shown in Fig. 7) are described in Table 12. Table 11 Eight Bit Any-PHY Bus Slave, Input Configuration
Byte
# bytes 53 54 54 55 55 55
0 Y Y Y Y Y Y
1 N N Y Y Y Y
2 N N N N Y Y
7 N Y N Y N Y
Register 0x0C H5UDF PRELEN
Notes
PHY ID byte, then H1-H4, no H5 byte Default setting. PHY ID, then H1-H5 PHY ID, 1 user byte then H1-H4 PHY ID, 1 user byte then H1-H5 PHY ID, 2 user bytes then H1-H4 PHY ID, 2 user bytes then H1-H5
0 1 0 1 0 1
00 00 01 01 10 10
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Table 12 Sixteen Bit Any-PHY Bus Slave, Input Configuration
Word
# bytes 54 56 56 58
0 Y Y Y Y
1 N N Y Y
4 N Y N Y
Register 0x0C H5UDF PRELEN
Notes
PHY ID word, then H1-H4, no H5/UDF field Default, PHY ID, H1-H4, then H5/UDF PHY ID, user word, then H1-H4, no H5/UDF PHY ID, user word, H1-H4, then H5/UDF
0 1 0 1
00 00 01 01
In the egress direction (cells are transferred from the LVDS to the output port), the port appears as a single addressable Any-PHY slave. The S/UNI-DUPLEX autonomously multiplexes the traffic from up to 32 logical channels and presents it as a single cell stream on the output bus. If at least one cell is present in any of the FIFOs, OCA will drive high when the device is polled. OCA is delayed by an additional clock cycle (one OFCLK) in the Any-PHY configuration. Polling occurs when OAVALID is sampled low and the sampled OADDR[4:0] matches the OAD[4:0] bits in the Output Address Match register. A cell transfer will be enacted if the OADDR[4:0] value equals the state of the OAD[4:0] bits in the Output Address Match register when the OENB is last sampled high. A word prepended to the transferred ATM cell identifies the logical channel. The three most significant bits of the prepend in the 8-bit format and the 11 most significant bits of the prepend in the 16-bit format are derived from the contents of the Extended Address Match registers, which default to all zeros. Table 13 summarizes the distinctions between the two protocols in the egress direction. Table 13 SCI-PHY/Utopia and Any-PHY Comparison, Egress Direction
Attribute Latency SCI-PHY/Utopia ODAT[15:0], OPRTY and OSOC are driven or become high impedance immediately upon sampling OENB low or high, respectively. OCA is driven immediately upon sampling a OADDR[4:0] value that matches the contents of the Output Address Match register. Undefined. It is low when not high impedance. Any-PHY 0DAT[15:0], 0PRTY, 0SOC and OSX are driven or become high impedance on the OFCLK rising edge following the one that samples OENB low or high, respectively. OCA is driven on the OFCLK rising edge following the one that samples a OADDR[4:0] value that matches the content of the Output Address Match register. High coincident with the first word of the cell data structure.
OSX
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OSOC Paused transfers
High coincident with the first word of the cell data structure. Permitted by deasserting OENB high, but the S/UNI-DUPLEX the address presented on OADDR[4:0] must match the content of the Output Address Match register the last cycle OENB is high to reselect the device. Not supported. A subsequent cell is output (provided one is available) if OENB is held low beyond the end of a cell.
High coincident with the second word of the cell data structure. Permitted by deasserting OENB high. The cell transfer resumes unconditionally when OENB is asserted low again.
Autonomous deselection
The outputs become high impedance after the last word of a cell is transferred until the S/UNI-DUPLEX is reselected.
The SCI-PHY/Any-PHY Output Configuration register (0x14) determines the cell format on the output bus. Byte 0 or Word 0 will always contain the channel ID. The cell length options for the 8 bit bus (shown in Fig. 6) are described in Table 14. 16 bit bus options (shown in Fig. 1) are described in Table 15. Table 14 Eight Bit Any-PHY Bus Slave, Output Configuration
Byte
# bytes 53 54 54 55 55 56
0 N N N N N N
1 N N Y Y Y Y
2 N N N N Y Y
7 N Y N Y N Y
Register 0x14 INADD H5 PRE UDF UDF LEN
Notes
PHY ID in byte 0, then H1-H4 Default setting. PHY ID , then H1H5 PHY ID, 1 user byte, then H1-H4 PHY ID, 1 user byte, then H1-H5 PHY ID, 2 user bytes, then H1-H4 PHY ID, 2 user bytes, then H1-H5
X X X X X X
0 1 0 1 0 1
00 00 01 01 10 10
Table 15 Sixteen Bit SCI-PHY/Utopia Bus Slave, Output Configuration
Word
# bytes 54 56 56 58
0 N N N N
1 N N Y Y
4 N Y N Y
Register 0x14 INADD H5 PRE UDF UDF LEN
Notes
PHY ID in word 0, then H1-H4 Default setting. PHY ID , H1-H4, then H5/UDF PHY ID , 2 user bytes, H1-H4 PHY ID , 2 user bytes, H1-H4, H5/UDF
X X X X
0 1 0 1
00 00 01 01
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Fig. 6 Eight Bit SCI-PHY/Utopia/Any-PHY Cell Format
Bit 7 W ord 0 (optional) W ord 1 (optional) W ord 2 (optional) W ord 3 W ord 4 W ord 5 W ord 6 W ord 7 (optional) W ord 8 Bit 5 Bit 4 Bit 0
Extended Address
PHYID[4:0]
User Prepend User Prepend H1 H2 H3 H4 H5 1 PAYLO AD1
W ord 55
PAYLOAD48
Note 1: Optionally, the H5 field can be overw ritten by the Extended Address and PHYID[4:0].
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Fig. 7 Sixteen Bit SCI-PHY/Utopia/Utopia Cell Format
Bit 15 W ord 0 (optional) W ord 1 (optional) W ord 2 W ord 3 W ord 4 (optional) W ord 5 W ord 6 H1 H3 H5 1 PAYLOAD1 PAYLOAD3 Extended Address User Prepend H2 H4 UDF 1 PAYLOAD2 PAYLOAD4 Bit 5 Bit 4 Bit 0
PHYID[4:0]
W ord 28
PAYLO AD47
PAYLOAD48
Note 1: O ptionally, the H5/UDF fields can be overwritten by the Extended Address and PHYID[4:0].
9.2
Clocked Serial Data Interface In some systems the PHY devices to which the S/UNI-DUPLEX is to interface may not contain an integrated Transmission Convergence function even though the low level protocol being transported over that interface is I.432 compliant ATM cells. For these types of devices (typically framers or modems) the S/UNIDUPLEX provides up to 16 bi-directional clocked serial data interfaces with fully integrated, I.432 compliant, Transmission Convergence (TC) functions to allow cell structured bit streams to be exchanged with the modems. The modems perform all Physical Media Dependent (PMD) functions so that the bit streams contain only contiguous ATM cells. The S/UNI-DUPLEX requires that the clock is gapped during PMD overhead bit locations.
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9.2.1 Upstream Functions In the upstream direction (input from the modems), the S/UNI-DUPLEX provides 2 inputs (clock and data) per channel and implements HCS cell delineation, payload descrambling, idle cell filtering and header error detection to recover valid ATM cells. These functions are performed in accordance with ITU-T Recommendation I.432.1. When configuring the S/UNI-DUPLEX in clocked serial data mode the user must modify the Transmit Logical Channel FIFO Depth register (0x5E) accordingly. See the register descriptions for details. Cell delineation is the process of framing to ATM cell boundaries using the header check sequence (HCS) field found in the ATM cell header. The HCS is a CRC-8 (x8 + x2 + x + 1) calculation over the first 4 octets of the ATM cell header. In accordance with ITU-T Recommendation I.432.1, the coset polynomial x6 + x4 + x2 + 1 is added (modulo 2) to the received HCS octet before comparison with the calculated result. When performing delineation, correct HCS calculations are assumed to indicate cell boundaries. The cell delineation circuitry performs a sequential bit-by-bit hunt for a correct HCS sequence. This state is referred to as the HUNT state. When a correct HCS is found, a particular cell boundary is assumed and the PRESYNC state is entered. This state verifies that the previously detected HCS pattern was not a false indication. If the HCS pattern was a false indication then an incorrect HCS should be received within the next DELTA cells and the delineation state machine falls back to the HUNT state. If an incorrect HCS is not found in this PRESYNC period then a transition to the SYNC state is made, cell delineation is declared and all non-idle cells with a correct HCS are passed on. In the SYNC state synchronization is not relinquished until ALPHA consecutive incorrect HCS patterns are found. In such an event a transition is made back to the HUNT state. The state diagram of the cell delineation process is shown in Fig. 8.
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Fig. 8 Cell delineation State Diagram
correct HCS (bit by bit)
HUNT
Incorrect HCS (cell by cell)
PRESYNC
ALPHA consecutive incorrect HCS's (cell by cell)
SYNC
DELTA consecutive correct HCS's (cell by cell)
The values of ALPHA and DELTA determine the robustness of the delineation method. ALPHA determines the robustness against false misalignments due to bit errors. DELTA determines the robustness against false delineation in the synchronization process. ALPHA is chosen to be 7 and DELTA is chosen to be 6. The loss of cell delineation (LCD) alarm is declared after a programmable threshold of incorrect cells occurs while in the HUNT state. The threshold is set by the Receive Serial LCD Count Threshold register. The threshold has a default value of 104 which translates to 73 ms at 600 kbs.All idle cells are filtered out and not passed to the high-speed interface. They are identified as cells containing all zeros VPI, and VCI fields and a one in the CLP bit. Optionally, unassigned cells (like idle cells except CLP is a zero) may also be filtered. All cells with an incorrect HCS octet are filtered out. Header correction is not implemented. As an option configured in Receive Serial Indirect Channel Configuration register (0x69), the ATM Transmission Convergence functions can be disabled to provide a clear channel capability. In this case, the serial data is segmented into 53 byte packets independent of the contents, and then transported across the highspeed LVDS links.
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9.2.2 Downstream Functions In the downstream direction (toward the modems), the S/UNI-DUPLEX uses one clock input and one data output per channel to produce valid ATM cell streams with correct HCS octets and inserted idle cells to adapt to the clock generated by the modem. Each modem provides its own clock, which may be asynchronous to all others. The S/UNI-DUPLEX responds to the active edge of each transmit clock by generating a single bit. Idle cells are automatically generated and interleaved with the cells available from the high-speed serial interface to match the channel's bit rate as driven by the clock input. When it needs to insert transmission overhead (such as framing bits) into the data stream provided by the S/UNI-DUPLEX, the modem is expected to gap the downstream clock provided to the S/UNI-DUPLEX so that no data bits are output during the overhead bit period(s). Optionally, the S/UNI-DUPLEX can be programmed (using register 0x74) to optionally force octet alignment of the data to overhead by monitoring the clock gaps. To support dynamically adaptable modem rate without external intervention, the system automatically adapts to frequency changes on LTXC[15:0]. When byte alignment is enabled, the clock gap period is monitored on each LTXC[15:0] input. If the gap period is greater than the minimum detectable period, the most significant bit of the data octet is output during the gap period, allowing the receiving modem to receive it on the first clock active edge after the gap. The S/UNI-DUPLEX can detect clock gaps of eight clock periods over the permitted LTXC[15:0] clock line frequency range. The frequency range over which one bit framing gap can be detected changes linearly with the speed of the high-speed links. When operating the LVDS interface at 200 Mb/s (REFCLK frequency set to 25 MHz), the S/UNI-DUPLEX will detect one bit clock gap for a line frequency range of 200 kHz to 8 MHz. At the minimum frequency of 100 Mb/s (REFCLK frequency of 12.5 MHz) the line frequency range at which one bit framing gap can be detected is 100 kHz to 4 MHz. As an option (see Transmit Serial Indirect Channel Data register 0x71) the transmitted data stream can be provided clear channel by disabling HCS generation and payload scrambling. It is the responsibility of the traffic generation entity at the other end of the LVDS link to send traffic at a sufficient rate to keep the internal FIFOs from emptying, else the clear channel data will be interrupted by an automatically generated ATM idle cell pattern.
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9.3
High-Speed Serial Interface The S/UNI-DUPLEX provides backplane interconnection via 100 to 200 Mb/s serial links. All data destined to and coming from the core cell processing card are concentrated on these high-speed links. The transceivers support UTP-5 cable lengths up to 10m. To avoid clock skew issues, no clock is transmitted and the receivers recover a local clock from the incoming data. Two bi-directional LVDS links are provided for redundancy; each link is intended to be routed to different core cards. Both LVDS transmitters carry identical traffic except for internally generated overhead. Both links are frequency locked to the single input reference clock although their phase is not guaranteed to match. At the LVDS receivers clock recovery and cell delineation are always active for both receivers to allow a quick switch to the redundant core card with minimal cell loss. The serial links carry ATM cells with prepended bytes. The cell format is illustrated in Fig. 9 and discussed in Section 12.2). The S/UNI-DUPLEX appends the first four bytes and the Header Check Sequence (HCS) byte in the upstream direction and strips them off and parses them in the downstream direction. The remainder of the bytes in the data structure are transferred transparently. The bytes are serialized most significant bit first. The bit stream is a simple concatenation of the extended cells. Cell rate decoupling is accomplished through introduction of stuff cells. The transmitter inserts a correct CRC-8 that protects both the ATM cell header and prepended bytes in the HCS byte. Cells with an errored HCS are counted and then discarded. The receiver also uses the HCS byte for determining cell delineation. Failure to establish cell alignment results in a loss of cell delineation 43 (LCD) alarm. The entire bit stream is scrambled with a x + 1 self-synchronous scrambler.Table 16 summarizes the contents of the system prepended bytes.
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Fig. 9 High-Speed Serial Link Data Structure
Byte
0
1
2
3 User Prepend
4+N User Header 4 to 6 bytes
H C S
Syste m Prepend
ATM Payload 48 bytes
ATM Payload
N bytes, where N = 0 or 2
Table 16 Prepended Fields Byte 0 1 Bits 7:0 7:0 Mnemonic CA[15:8] CA[7:0] Description The CA[15:0] bits carry per-PHY flow control information in the upstream direction. To support 32 PHYs, the status for each PHY is sent every other cell; the CASEL indicates which half is represented. If CASEL is logic 0, CA[15:0] corresponds to those PHYs with addresses 0 through 15. If CASEL is logic 1, CA[15:0] corresponds to those PHYs with addresses 16 through 31. In the downstream direction, CA[15:0] communicates congestion of the upstream entity. The encoding is identical to the upstream direction. A logic 0 indicates the far end can accept no more cells for a specific logical channel. A logic 1 indicates the S/UNI-DUPLEX is free to send queued traffic for that logical channel immediately. In the event of an errored header (as detected by an incorrect HCS), the CA bits will be assumed to be all zero. This ensures cells are not transmitted for which there is no buffer space. 2 7 CASEL The state of the CA select bit determines which half of the PHY devices the CA[15:0] bits correspond to. CASEL toggles with each cell transmitted.
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Byte 2
Bits 6
Mnemonic UPCA
Description The UPCA bit carries flow control information for the microprocessor control channel. If this bit is one, control channel cells may be transferred. In the event of an errored header, the UPCA bit will be assumed to be zero. This ensures cells are not transmitted for which there is no buffer space.
2
5:0
PHYID
The PHY identifier determines to which PHY a cell is destined in the downstream direction and from which PHY it came in the upstream direction. It also indicates whether the cell is a stuff or control channel cell. The field is encoded as follows: "111111" - Stuff cell provided for cell rate decoupling. The payload carries no useful data and the cell shall be discarded. "111110" - Control channel cell. On the transmit serial link, PHYID shall equal this value for all cells inserted via the Microprocessor Cell Buffer. All cells received on the serial link with this encoding will be routed to the local microprocessor. "100000" to "111101" - Reserved "000000" to "011111" - Logical channel index for the PHY devices.
3
7
BOC
The Bit Oriented Code (BOC) bit position carries a repeating 16 pattern that encodes one of 63 possible code words used for remote control and status reporting. Five codes are predefined to represent a remote defect, a loopback activate request, a loopback deactivate request, a reset activate request and a reset deactivate request. The remaining codes are either reserved or user defined. The receiver ensures the pattern is the same for 10 (default) or 5 repetitions before
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Byte
Bits
Mnemonic
Description validating a new code word. Refer to the 9.3.1 section for more details. The link active bit indicates which of the redundant links is currently chosen. The S/UNI-DUPLEX will switch to the link which contains a one in this location for at least 3 consecutive cells. The local microprocessor can override this selection. If both links present a one in this location, the selection remains unchanged. To confirm which link is active, the transmitted ACTIVE bit will be a one if the associated receive link is selected. In the event of an errored header, the previous ACTIVE value is retained.
3
6
ACTIVE
3
5:0
TREF[5:0]
The timing reference encodes an 8 kHz signal inband that is independent of the serial bit rate. The TREF[5:0] binary value represents the number of high-speed link bytes after this one at which the timing reference is inferred. An all ones value indicates no timing mark is associated with this cell.
The transmitter outputs are internally terminated current mode drivers. Correct termination is at the receiver required to provide appropriated signal levels. The internal transmit clock is synthesized from a 12.5 MHz to 25 MHz clock. The resulting data bit rate is eight times the frequency of the REFCLK input. All jitter below 1 MHz on REFCLK is passed unattenuated to the TXD1+/- and TXD2+/outputs. The design of the loop filter and PLL is optimized for minimum intrinsic jitter. With a jitter free reference input and a low noise board layout, the intrinsic jitter is typically less than 0.01 UI RMS and 0.10 UI peak-to-peak when measured using a band pass filter with 12 kHz and 1.3 MHz cutoff frequencies. The two truly differential receivers are capable of handling signal swings down to 100mV. A wide common mode range makes them compatible with LVDS signals. External termination resisters must be provided to match the cable impedance.
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The receivers monitor for loss of signal (LOS) on the links. LOS is declared upon 2048 bit periods (13.2 s at 155.52 Mb/s) without a signal transition in the scrambled data. As a consequence, a status bit is set, a maskable interrupt is asserted and the RDI (Remote Defect Indication) codeword is sent repetitively in the BOC bit in the corresponding downstream link. The LOS indication is cleared when a signal transition has occurred in each of 16 consecutive intervals of 16 bit periods each. Clock recovery is performed by a digital phase locked loop (DPLL). The implementation is robust against operating condition variations and power supply noise. The receive link is constrained to be within 100 ppm of eight times the REFCLK frequency. As shown in Fig. 10, two datapath loopbacks are provided on each LVDS link to aid in fault isolation and continuity verification. The metallic loopback routes high-speed serial receive data to the transmitter. The diagnostic loopback replaces the downstream data with the upstream data. The loopbacks can be enabled individually or simultaneously, and each link can be looped back independently of the other.
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Fig. 10 Datapath Loopback
RSTO B RCLK RX8K TX8K
SC IANY OBUS8 OA NYPH Y OMAS TER OENB OADDR[4:0] OAVALID ODAT[15:0] OPR TY OSOC OSX OFCLK OCA
SCI-PHY Transm it Master/ Receive Slave
LTXD [15:0] LTXC [15:0] LRXD[15:0] LRXC[15:0] IBUS 8 IAN YPH Y IMASTER IEN B IADDR[4:0] IAVALID IDAT[15:0] IP R TY ISOC ISX IFCLK IC A A[8:0] RDB W RB CSB ALE IN TB RS TB D[7:0] to all blocks MicroProcessor Interface
Elastic Store
Tim e-Sliced AT M Transm ission Convergence
per-PHY buffers Cell Processor per-PHY buffers
RXD1+ RXD1TXD 1+ TXD 1RXD2+ RXD2TXD 2+ TXD 2-
SCI-PHY Receive Master/ Transm it Slave
2 Cell Buffer 4 Cell FIFO
Clock Synthesis
REFCLK
JTAG Test Access Port
TD O TD I TC K TM S TR S TB
A diagnostic loopback is effected if the DLB bit of the Serial Links Maintenance register (0x05) corresponding to the active high-speed serial link is set to logic 1 (DLB1 or DLB2 depending if data is being received from the RXD1+/- or RXD2+/inputs). The upstream data and clock are inserted into the downstream datapath
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DUAL SERIAL LINK PHY MULTIPLEXER
after clock recovery. Setting the DLB bit corresponding to the inactive link has no effect. The metallic loopback is set independently on each high-speed serial link. It can be effected in one of three ways: after the receipt of the loopback activate code on the corresponding RXD1+/- or RXD2+/- inputs (as described in Section 9.3.2) when the corresponding MLB1 or MLB2 bit of the Serial Link Maintenance register is set to logic 1 or when the reset (RSTB) input is asserted low. The loopback occurs at the LVDS transceiver after the conversion to digital but before clock recovery. The looped back data may be slightly distorted by the data slicing (differential to single-ended) and re-buffering that occurs. Metallic loopback is terminated if a loopback deactivate bit oriented code is received and validated, provided the corresponding MLB1 or MLB2 bit of the Serial Links Maintenance register to logic 0. 9.3.1 Link Integrity Monitoring Although the serial link bit error rate can be inferred from the accumulated Header Check Sequence (HCS) errors, the option exists to perform error monitoring over the entire bit stream. When the feature is enabled the second User Prepend byte transmitted shall be overwritten by the CRC-8 syndrome for the preceding cell. The encoding is valid for all cells, including stuff cells. The CRC-8 polynomial is x8 + x2 + x + 1. The receiver shall raise a maskable interrupt and optionally increment the HCS error count. Simultaneous HCS and cell CRC-8 errors result in a single increment. 9.3.2 Bit Oriented Codes Bit Oriented Codes (BOCs) are carried in the BOC bit position in the System Prepend. The 63 possible codes can be used to carry predefined or user defined signaling. Bit oriented codes are transmitted as a repeating 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). The code to be transmitted is set independently on the two LVDS links, and is programmed by writing the TXD1 Bit Oriented Code and TXD2 Bit Oriented Code registers. The autonomously generated Remote Defect Indication (RDI) code, which is generated upon a loss-of-signal or loss-of-cell-delineation, takes precedence over the programmed code. RDI insertion can be disabled via the RDIDIS bit of the Serial Links Maintenance register. RDI can be inserted manually on a highspeed serial link by setting the corresponding TXD1 Bit Oriented Code or TXD2 Bit Oriented Code register to all zeros.
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The receiver can be enabled to declare a received code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the Bit Oriented Code Receiver Enable register. Unless fast declaration is necessary, it is recommended that the AVC bit be set to logic 0 to improve bit error tolerance. Valid BOC are indicated through the RXD1 Bit Oriented Code Status and RXD2 Bit Oriented Code Status registers. The BOC bits are set to all ones (111111) if no valid code has been detected. A maskable interrupt is generated to signal when a detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits go to all ones). When the receiver is out of cell delineation (OCD), the BOC detection is disabled and the corresponding RXD1 or RXD2 Bit Oriented Code Status register will produce all ones (111111). . The valid codes are provided in Table 17. The Reserved codes anticipate future enhanced feature set devices and should not be used. The User Defined codes may be used without restriction. Regardless of definition, all 63 codes may be validated and read by a microprocessor. Only four codes result in autonomous action: loopback activate, loopback deactivate, reset output activate and reset output deactivate. Note that processing of the metallic loopback activate code is handled as a special case. The RXD1+/-, RXD2+/- data is looped back onto TXD1+/-, TXD2+/- respectively at the end of the reception of the loopback activate code on the corresponding high-speed serial link rather than when the code is first validated. For the loopback to be enabled the loopback code must be first validated (received 8 out of 10 times at least once) and then invalidated, typically by reception of another code. The loopback is not enable upon initial validation of the loopback activate code because the looped back signal, which still contains the original loopback activate command, would cause the far-end receiver to go into metallic loopback, thereby forming an undesirable closed loop condition! The loopback is cleared immediately upon the validation of the loopback deactivate code, assuming the corresponding MLB register bit of the Serial Links Maintenance register is logic 0. To produce a loopback at the far end, program the desired TXD1 Bit Oriented Code or TXD2 Bit Oriented Code register with the loopback activate code for at least 1 ms and then revert to another (typically idle) code. Upon termination of the loopback activate code, the data transmitted on TXD1+/- or TXD2+/- is expected to be received verbatim on the RXD1+/- or RXD2+/- inputs. When transmitting a loopback activate code on a high-speed serial link, it is recommended the corresponding RDIDIS1 or RDIDIS2 register bit be set to logic 1, or else a loss-of-signal or loss-of-cell-delineation event would cause a premature loopback due to a pre-emptive Remote Defect Indication (RDI) code being sent.
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The remote reset activate and remote reset deactivate code words are used to control the RSTOB output. If the remote reset activate code is validated, the RSTOB output is asserted low. If the remote reset deactivate code is validated the RSTOB output becomes high impedance. RSTOB can also be controlled through the RESETO bit in the Master Configuration register. The Remote Defect Indication (RDI) is sent whenever Loss of Signal (LOS) or Loss of Cell Delineation (LCD) is declared. This code word takes precedence over all others. Table 17 Assigned Bit Oriented Codes Function Remote Defect Indication (RDI) Loopback activate Loopback deactivate Remote reset activate Remote reset deactivate Reserved ... Reserved User Defined ... User Defined Idle Code 9.3.3 Cell Delineation Process The S/UNI-DUPLEX performs HCS cell delineation, payload descrambling, idle cell filtering and header error detection to recover valid cells from the receive high-speed links. These functions are performed with a similar algorithm as for the upstream Clocked Serial Data interface described in Section 9.2.1 but support 9 to 13 byte cell headers. The loss of cell delineation (LCD) alarm is declared after 1318 consecutive cell periods (4.0 ms at 155.52Mb/s) in the HUNT or PRESYNC states. The LCD alarm is cleared after 1318 consecutive cells in the SYNC state. Codeword (left bit transmitted first) 11111111 00000000 11111111 01000000 11111111 00100000 11111111 01100000 11111111 00010000 11111111 01010000 ... 11111111 00000100 11111111 01000100 ... 11111111 00111110 11111111 01111110
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9.3.4 Protection Switching Protocol The S/UNI-DUPLEX and its sister device, the S/UNI-VORTEX inherently support system architectures requiring fault tolerance and 1:1 redundancy of the system's common equipment. In point-to-point backplane architectures such as these, the 1:1 protection also includes the associated LVDS links connecting the common equipment to the line cards. The S/UNI-VORTEX and S/UNI-DUPLEX perform clock recovery, cell delineation, and header error monitoring for all receive high-speed serial links simultaneously. The maintained error counts and alarm status indications may be used by the control system to determine the state and viability of each LVDS link. See the S/UNI-VORTEX data sheet for additional details. In these architectures, each S/UNI-DUPLEX will be connected to two S/UNIVORTEXs (see Fig. 1) or to two S/UNI-DUPLEXs (see Fig. 5). Upon a failure of the active card, the spare card becomes the conduit for traffic. The S/UNIVORTEX and S/UNI-DUPLEX facilitate link selection upon start-up as well as switching between links upon failure conditions. Typically a centralized resource or cooperating distributed microprocessor subsystems will determine which common card is to be considered active for each downstream S/UNI-DUPLEX and sets the active indication accordingly. The current state of the link's active bit is sent downstream once per transmitted cell. The active status is debounced and acted upon by the far-end S/UNIDUPLEX. The S/UNI-DUPLEX will only accept data traffic from one of its two LVDS links, and normally it is the link marked active that is considered the working link (although this can be overridden locally as discussed below). Thus, although the far-end S/UNI-VORTEX or S/UNI-DUPLEX may indicate the desired active and spare links, it is actually the local S/UNI-DUPLEX that must enforce the protection switching. The link switching mechanism preserves cell integrity on the high-speed serial link that becomes active. In other words, switching occurs between cells. At reset Link 1 is marked as the active link. It is also important to note that a Loss of Signal (LOS) on the active LVDS link does not automatically affect the value of the ACTIVE bit. The ACTIVE bit value prior to the LOS condition is maintained unless the other link's active indication is asserted (after debouncing) or until a local override (described below) or device reset is invoked. The value of the extracted ACTIVE bit is forced to logic 0 when the corresponding link is in Loss of Cell Delineation (LCD ) state. If the S/UNI-DUPLEX is auto-selecting its active link status (Master Configuration register 0x01, RXAUTOSEL = 1) the active bit transmitted on the two LVDS links
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will indicate which link is currently chosen as active. This reflected ACTIVE bit may not have a direct affect on the far end S/UNI-VORTEX or S/UNI-DUPLEX, but its status is typically debounced (must remain the same for 3 received cells) and then stored by the far end device. The reflected status is normally monitored by the control system to determine when protection switching has been completed. The S/UNI-DUPLEX stores its LVDS active indication in the ACTIVE bit in Master Configuration register (0x01). The S/UNI-DUPLEX can override active link selection in the receive direction or force link selection in the transmit direction (this applies to the S/UNI-DUPLEX to S/UNI-DUPLEX type configuration) using the Master Configuration register (0x01). If the S/UNI-DUPLEX is forcing its ACTIVE link status (Master Configuration register 0x01, RXAUTOSEL = 0) the active receive link and the transmitted ACTIVE bit on the two LVDS links will reflect the status of the Master Configuration register ACTIVE bit. If ACTIVE is 0 then LVDS link 1 receiver will be active and link 1 transmitter will indicate it is active, while LVDS link 2 transmitter will indicate it is inactive. If the ACTIVE bit is 0 the opposite indications will occur. 9.4 Cell Buffering and Flow Control The possibility of congestion is inherent in an access multiplexer. In the downstream direction, the WAN link can generate a burst of cells for a particular PHY device at a rate far exceeding the modem's bandwidth capacity. Therefore, feedback to the core card is required to cause it to buffer and smooth cell bursts to prevent downstream buffer overflow. In the upstream direction, the subscribed aggregate bandwidth can exceed that accommodated by the WAN uplink. Flow control is required to ensure fair access to the uplink, to minimize cell loss and to minimize the impact of greedy users on others. 9.4.1 LVDS Receive Traffic Flow Control In the LVDS receive direction the primary task of the S/UNI-DUPLEX is to accept cells from the active high speed link, inspect the PHYID field to determine the destination of the cell, and then route the cell to the appropriate parallel bus PHY, clocked serial data interface, or to the microprocessor port. Because the LVDS link typically supports a much higher transfer bandwidth than the external devices, rate decoupling and flow control are implemented. Flow control signaling is implemented using in-band system overhead appended to each cell sent over the LVDS link (see Table 16). On the currently active link user cells (those destined to the parallel bus or clocked serial data interfaces) and inter-processor communication channel cells (those destined to the microprocessor port) are processed. On the inactive link only inter-processor communication cells (hereafter called control cells) are
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processed - user cells are discarded. Both links discard stuff cells after extracting the system overhead. The active link uses all fields of the system overhead on each cell. The inactive link monitors the PHYID (only to identify control channel cells), the ACTIVE, BOC, and TREF fields. Both links monitor for loss of signal and loss of cell delineation conditions. Cells received with an incorrect Header Check Sequence (HCS) (due to bit errors during transmission) are counted and discarded. The system overhead fields of errored cells are ignored. User and control channel cells received from the high-speed serial link are temporarily stored in a shallow buffer partitioned into a separate FIFO for each logical channel. As discussed below, cells are read out of this buffer under the control of the parallel bus, the clocked serial data, or the microprocessor interface. The buffer is logically partitioned into a FIFO for each logical channel. Each FIFO has an associated flow control bit (CA for user cells, UPCA for the control channels) embedded within the prepended bytes in the upstream highspeed serial link. The 34 (32 PHYs + 2 control channels) channel FIFOs are four cells deep. When a FIFO contains less than two cells, the corresponding flow control bit is set to allow cell transmission. Upon the beginning of the write of a cell which will place the second cell in the FIFO, the flow control bit becomes a zero until only one cell remains in the FIFO. The far end device (either another S/UNI-DUPLEX or a S/UNI-VORTEX) will only resume sending cells to that PHY or control channel when its flow control bit has been set to a one. Since the flow control bit is encoded into the next upstream cell (either a user data cell or a filler cell) there will be some latency between the setting and clearing of the flow control bit and the corresponding action by the far-end device. However, since the far-end buffer is four cells deep no overflow condition will occur. The process of reading cells out of the per channel FIFOs and placing them on the parallel bus is flow controlled by the bus polling protocol, as discussed in Section 9.1. When operating with the clocked serial data interface, cells are read from the FIFO at a rate determined by the transmit clock provided to the S/UNIDUPLEX by the modem. If the FIFO contains less than one complete cell when the previous cell has been serialized then an idle cell will be emitted. Idle cell generation has no impact of the channel's FIFO. See Section 9.7.1 for a description of how the two control channel interfaces are presented to the microprocessor port. 9.4.2 LVDS Transmit Traffic Flow Control In the LVDS transmit direction, the primary task of the S/UNI-DUPLEX is accept cells from the parallel bus, clocked serial interfaces, or microprocessor port
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control channel, add system overhead to the cell (including the PHY ID), and then transmit the cell over both high speed links simultaneously. Per PHY rate decoupling and flow control are implemented to ensure head-of-line blocking and far-end buffer overflow never occur. Flow control signaling is implemented using in-band system overhead appended to each cell sent over the LVDS link (see Table 16). The transmitted cell is identical on both links except for the ACTIVE field, the BOC bit and UPCA status field. Stuff cells are automatically generated and sent over the high speed link if there is no user data cell or control channel cell to send or if the far-end is indicating that it has no room in any of its per channel buffers. It is important to note that the S/UNI-DUPLEX only acts on the CA and UPCA status fields of the active LVDS receive link. The inactive link's flow control information is ignored. This should be taken into account when designing 1:1 protected systems, especially with respect to the behavior of the standby common card data path and the embedded control channel. Rate decoupling between the external PHYs and the LVDS link occurs via the per channel buffers. Specifically, independent internal processes determine how the buffers are filled and how they are scheduled onto the LVDS link. When the S/UNI-DUPLEX is configured as a parallel bus master the 32 PHY devices are polled in a round robin fashion. When a polled external PHY indicates that it has a cell available the cell is transferred into a shallow FIFO. Each PHY has its own FIFO. If the per-channel flow control asserted by the farend prevents cells from being transferred from a buffer to the LVDS transmit link, the buffer may fill to capacity, at which time the S/UNI-DUPLEX will remove that external PHY from the polling sequence until buffer space becomes available. Under congestion the S/UNI-DUPLEX does not discard cells, although the external PHY device may have to. When the S/UNI-DUPLEX is configured as a parallel bus slave the PHY devices are polled by the bus master and the S/UNI-DUPLEX provides the appropriate FIFO status indication, as described in Section 9.1.2 and Section 9.1.3. If the per-channel flow control asserted by the far-end prevents cells from being transferred from a buffer to the LVDS transmit link, the buffer may fill to capacity, at which time the S/UNI-DUPLEX will deassert the buffer available status for that PHY when it is polled. Under congestion the S/UNI-DUPLEX does not discard cells, although the external bus master may have to. When the S/UNI-DUPLEX is configured for clocked serial data interfaces, cells from the maximum 16 PHYs are buffered in 16 dedicated logical channel FIFOs. They should be programmed in the Transmit Logical Channel FIFO Depth
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register (0x5E) to be four cells deep as per the I.432 specification. If flow control asserted by the far-end device prevents cells from a particular serial data interface from being read, the corresponding FIFO will begin to fill. In general, proper system engineering should ensure that the far-end is able to keep up, but should flow control continue to be asserted by the far-end an overflow condition could occur. Overflow results in an optional interrupt being raised, an error status register being set, and subsequently received cells being discarded until FIFO space is available. Regardless of whether configured a bus master, bus slave, or clocked serial data device, the S/UNI-DUPLEX monitors the per-channel FIFOs and performs round robin scheduling of cells onto the transmit LVDS links. The control channel FIFO is given equal priority to the PHYs.
The device attached to the far-end of the LVDS link is typically a S/UNI-VORTEX (see Fig. 1) or a S/UNI-DUPLEX (see Fig. 4 and Fig. 5). Although the S/UNIDUPLEX only implements one form of transmit flow control, to help understand the end-to-end flow control we will discuss the two situations separately. Case #1: the far-end device is a S/UNI-VORTEX The S/UNI-VORTEX is a parallel bus slave with a single receive buffer for each of its eight LVDS links. It uses a weighted round robin polling of these buffers and schedules the received cells onto the parallel bus under the control of the bus master. The S/UNI-VORTEX's eight LVDS links running at 200 Mb/s can provide aggregate traffic bursts that exceed the capacity of a 800 Mb/s parallel bus. Also, link polling weights may be set such that one or more links receive relatively less of the aggregate bus bandwidth. Therefore, it is quite likely that congestion will sometimes occur at the S/UNI-VORTEX's LVDS receive buffers. Since all traffic received on the eight LVDS links is heading to the S/UNIVORTEX's parallel bus there was no need to partition this FIFO into individual channels. Therefore the S/UNI-VORTEX implements flow control on each of its LVDS links in a binary fashion - all 32 logical channels are enabled or all channels are disabled. The S/UNI-VORTEX may or may not treat the microprocessor control channel independently from the user channels depending on how it is configured. If it is programmed to route control channel cells out over the parallel bus then the control channel flow control is identical to the 32 user channels. If the control channel is being routed to the microprocessor port then the control channel flow control is independent from the user channels. When the S/UNI-VORTEX's LVDS receiver cell buffer becomes congested the S/UNI-VORTEX will immediately clear the CA bits and possibly the UPCA fields in Table 16 in the cells sent on the downstream LVDS link. When the S/UNI-
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DUPLEX sees that all far-end channels are congested it will immediately start sending stuff cells on the upstream serial link (unless it has control channel cells to send and that channel is not marked as congested). With the worst case alignment between upstream and downstream links, the S/UNI-DUPLEX may transmit up to two cells after the cell available deassertion was first registered by the far-end S/UNI-VORTEX. The FIFO threshold on the S/UNI-VORTEX accounts for this latency, buffer overflow cannot occur. Once the far-end S/UNI-VORTEX has a chance to clear cells from its receiver buffer it will reassert the cell available bit on all channels. Refer to the S/UNIVORTEX Data Sheet for further information. Case #2: the far-end device is a S/UNI-DUPLEX Unlike the S/UNI-VORTEX, the far-end's S/UNI-DUPLEX's LVDS receive buffer is divided into 32 FIFOS, so it always individually indicates the status of the 32 user channels. This also applies to the control channel - its status in independent of the status of the user channels. When the near-end S/UNI-DUPLEX sees that a PHY or control channel is congested it will take that channel out of the round robin scheduling used to transfer cells from the buffers to the transmit LVDS link. If none of the remaining channels have cells to send, or if all channels are experiencing congestion, then the S/UNI-DUPLEX will automatically broadcast a stuff cell on the two upstream serial links. With worst case alignment between upstream and downstream links, the S/UNIDUPLEX may transmit up to two cells to a channel after the cell available deassertion for that channel was first registered by the far-end S/UNI-DUPLEX. Since the FIFO threshold on the S/UNI-DUPLEX accounts for this latency, buffer overflow cannot occur on the active link. Once the far-end S/UNI-DUPLEX has a chance to clear cells from the congested receive buffer it will reassert the cell available bit on the affected channel. 9.5 Timing Reference Insertion and Recovery The high-speed serial links are capable of transporting a timing reference independent of the bit rate. The timing signal received on the active RXD1+/- or RXD2+/- inputs is presented on RX8K. Rising edges of TX8K input are encoded in the TXD1+/- and TXD2+/- cells. Although the timing reference is targeted at a typical need of transporting an 8 kHz signal, its frequency is not constrained to 8 kHz. Any frequency less than the cell rate is permissible.
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The rising edge of TX8K initializes an internal counter to the number of bytes in the high-speed serial cell minus one. The counter decrements with each byte transmitted. Upon the fourth byte of the next extended cell, the state of the counter is encoded in the TREF[5:0] field. If no rising edge on TX8K has occurred, TREF[5:0] is set to all ones. In the receive direction, two independent counters are initialized to the value of TREF[5:0] extracted from RXD1+/- or RXD2+/-. The counters decrement with each byte received on its respective high-speed serial link. When the count becomes zero, a rising edge is generated on an internal reference signal associated to this counter. If the value of TREF[5:0] is all ones, the signal remains low. The internal reference signal of the high-speed serial link that is declared active is output on RX8K. If the same functionality is implemented at the far end of the serial link, it can be seen that the recovered timing event is generated one cell period later than the inserted timing with a resolution of one byte. Because of the limited edge encoding resolution, some jitter is present. At a link rate of 155.52 Mb/s, 63ns of peak-to-peak jitter will occur on RX8K. A local high-Q phase locked loop (PLL) can be used to remove the jitter. In systems where 1:1 protection is used the timing reference output on TX8K will change sources if the link marked active changes. Even though the S/UNIDUPLEX maintains the edges being sent on both links, and even if the far end sources are synchronized, there is no guarantee that an arbitrary phase hit will not occur during protection switching. In general the LVDS links will run error free, but if errors do occur the S/UNIDUPLEX discards a cell that arrive with an HCS error. Hence it is possible that a transmission error could corrupt the cell carrying a clock edge indication in TREF[5:0]. This would result in that edge being lost (i.e. there would be no corresponding output on TX8K). 9.6 JTAG Test Access Port The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The S/UNI-DUPLEX identification code is 173500CD hexadecimal. 9.7 Microprocessor Interface The microprocessor interface is provided for device configuration and status monitoring by an external microprocessor. Normal mode registers and test mode
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registers can be accessed through this port. Test mode registers are used to enhance the testability of the S/UNI-DUPLEX. The interface has a 8-bit wide data bus. Multiplexed address and data operation is supported. 9.7.1 Inband Communication A cell insertion and extraction capability provides a simple unacknowledged cell relay capability. For a fully robust control channel implementation, it is assumed the local microprocessor and the remote entity are running a reliable communications protocol. In the upstream direction, identical copies of each control channel cell are broadcast on both the active and spare high-speed serial links. If the user wishes to implement two independent control channels (active/inactive or link 1/link 2) then the contents of the cell will have to indicate the cell's destination link. In the downstream direction, each high-speed serial link has a dedicated receive queue for the control channel cells. The control channel is treated as a virtual PHY device. In the upstream direction, it is scheduled with the same priority as the other logical channels. Flow control with the receiving device (either a S/UNI-VORTEX or a S/UNIDUPLEX) is based on the cell available bit (UPCA, see Table 16) of the highspeed serial link marked as active. In the downstream direction, control channel cells are queued in a four cell FIFO for each high-speed serial link. If either FIFO contains two or more cells, the cell available bit returned upstream on the corresponding high-speed link is deasserted to prevent cell loss when the microprocessor cell reads fail to keep pace with the incoming control channel cells. 9.7.2 Writing Cells The S/UNI-DUPLEX contains a two cell buffer for the insertion of a cell by the microprocessor into the high-speed serial interface. Optional CRC-32 calculation over the last 48 bytes of the cell relieves the microprocessor of this task. The CRC-32 generator polynomial is consistent with AAL5: 5. G(x) = x +1
32
+ x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x
All cells written by the microprocessor will have binary 111110 encoded in the PHYID[5:0] field within the cell prepend bytes. This distinction between user cells and control cells provides a clear channel for both types of cells.
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The microprocessor cell format is illustrated in Fig. 11. The 8-bit cell data structure is fixed at 60 bytes long regardless of how the SCI-PHY/Utopia/AnyPHY bus (or the Clocked Serial Data interface) and LVDS link are configured. The microprocessor must transfer all bytes of the cell, including the unused ones. The unused bytes are included in the received cell when it is made available to the far-end microprocessor, but the value of the bytes is undefined. This 60 bytes cell format is used to retain interface compatibility with the PM7326 S/UNI-APEX device, and to align the header and data fields on 32 bit boundaries. Bytes marked with an asterisk in Fig. 11 must be included in cells written into the cell transfer register, but they will only be sent across the LVDS if the corresponding Transmit High-Speed Serial Configuration register (0x60) and the far-end's corresponding Receive High-Speed Serial Configuration register have been programmed to include them. See Section 12.2 for details. Other than what has already been mentioned, there are no constraints on the contents of cells written by the microprocessor. They are transported across the LVDS link transparently. Specifically, although the standard ATM header bytes H1-H5 are shown in Fig. 11 there is no restriction on the values they can contain. See Section 12.1.1 for details on the cell write protocol.
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Fig. 11 Microprocessor Cell Format
Bit 7 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Byte 8 Byte 9 Byte 10 Byte 11 Byte 12 Unused Unused User Prepend * User Prepend* H1 H2 H3 H4 H5* UDF * Unused Unused PAYLOAD1 Bit 0
Byte 59
PAYLO AD48
*Depending on the serial link program m ing, these fields m ay be undefined or not transm itted.
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9.7.3 Reading Cells The microprocessor cell buffer has a capacity of four cells. The UPCA bit returned on the upstream high-speed serial link will be set to logic 0 when the buffer contains more than two cells. This shall prevent overflow of the local buffer if the indication is responded to within two cell slots. Maskable interrupt status bits are generated upon the receipt of the first cell, upon detection of a CRC-32 error and upon a buffer overflow. If a buffer overflow occurs (this would indicate an operation failure due to the far-end device not respecting the UPCA bit status), entire cells are lost (the new incoming cells would be lost). The format of received cell when it is read from the Microprocessor Cell Buffer Data register is shown in Fig. 11. Unused bytes have undefined value. The value of the bytes marked with an asterisk depends on the configuration of the corresponding LVDS link and the source of the cell. This is discussed further in the Operations section. See Section 12.1.2 for details on the cell read protocol. 9.8 Internal Registers The microprocessor interface provides access to normal and test mode registers. The normal mode registers are required for mission mode operation, and test mode registers are used to enhance the testability of the S/UNI-DUPLEX. The register set is accessed as follows: 9.9 Register Memory Map
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B
Register Master Reset and Identity / Load Performance Meters Master Configuration Master Interrupt Status Miscellaneous Interrupt Statuses Clock Monitor Serial Links Maintenance Extended Address Match (LSB) Extended Address Match (MSB) Extended Address Mask (LSB) Extended Address Mask (MSB) Output Address Match Configuration Pins Status
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0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0X16 - 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E - 0x2F 0x30 0x31 0x32 - 0x33 0x34 0x35
SCI-PHY/Any-PHY Input Configuration 1 SCI-PHY/Any-PHY Input Configuration 2 SCI-PHY/Any-PHY Input Interrupt Enables SCI-PHY/Any-PHY Input Interrupt Status Input Cell Available Enable (LSB) Input Cell Available Enable (2nd) Input Cell Available Enable (3rd) Input Cell Available Enable (MSB) SCI-PHY/Any-PHY Output Configuration SCI-PHY/Any-PHY Output Polling Range Reserved RXD1 Bit Oriented Code Enable RXD1 Bit Oriented Code Status RXD2 Bit Oriented Code Enable RXD2 Bit Oriented Code Status Reserved TXD1 Bit Oriented Code Reserved TXD2 Bit Oriented Code Microprocessor Cell Buffer Interrupt Microprocessor Insert FIFO Control Microprocessor Extract FIFO Control Microprocessor Insert FIFO Ready Microprocessor Extract FIFO Ready Insert CRC-32 Accumulator (LSB) Insert CRC-32 Accumulator (2nd byte) Insert CRC-32 Accumulator (3rd byte) Insert CRC-32 Accumulator (MSB) Extract CRC-32 Accumulator (LSB) Extract CRC-32 Accumulator (2nd byte) Extract CRC-32 Accumulator (3rd byte) Extract CRC-32 Accumulator (MSB) Microprocessor Cell Buffer Data Reserved RXD1 Extract FIFO Control RXD1 Extract FIFO Interrupt Status Reserved RXD2 Extract FIFO Control RXD2 Extract FIFO Interrupt Status
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0x36 - 0x3B 0x3C 0x3D 0x3E - 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 - 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 - 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D
Reserved Receive Logical Channel FIFO Control Receive Logical Channel FIFO Interrupt Status Reserved RXD1 High-Speed Serial Configuration RXD1 High-Speed Serial Cell Filtering Configuration/Status RXD1 High-Speed Serial Interrupt Enables RXD1 High-Speed Serial Interrupt Status RXD1 High-Speed Serial HCS Error Count RXD1 High-Speed Serial Cell Counter (LSB) RXD1 High-Speed Serial Cell Counter RXD1 High-Speed Serial Cell Counter (MSB) Reserved RXD2 High-Speed Serial Configuration RXD2 High-Speed Serial Cell Filtering Configuration/Status RXD2 High-Speed Serial Interrupt Enables RXD2 High-Speed Serial Interrupt Status RXD2 High-Speed Serial HCS Error Count RXD2 High-Speed Serial Cell Counter (LSB) RXD2 High-Speed Serial Cell Counter RXD2 High-Speed Serial Cell Counter (MSB) Reserved Transmit Logical Channel FIFO Control Transmit Logical Channel FIFO Interrupt Status Transmit Logical Channel FIFO Depth Reserved Transmit High-Speed Serial Configuration Transmit High-Speed Serial Cell Count Status Transmit High-Speed Serial Cell Counter (LSB) Transmit High-Speed Serial Cell Counter Transmit High-Speed Serial Cell Counter (MSB) Reserved Receive Serial Indirect Channel Select Receive Serial Indirect Channel Configuration Receive Serial Indirect Channel Interrupt Enables Receive Serial Indirect Channel Interrupt and Status Receive Serial Indirect Channel HCS Error Count Receive Serial LCD Count Threshold
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0x6E - 0x6F 0x70 0x71 0x72 - 0x73 0x74 0x75 - 0x7F 0x80 - 0xFF
Reserved Transmit Serial Indirect Channel Select Transmit Serial Indirect Channel Data Reserved Transmit Serial Alignment Control Reserved Reserved for test registers
For all register accesses, CSB must be low.
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10
NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the S/UNI-DUPLEX. Normal mode registers (as opposed to test mode registers) are selected when TRS (A[8]) is low. Notes on Normal Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. All configuration bits that can be written into can also be read back. This allows the processor controlling the S/UNI-DUPLEX to determine the programming state of the block. 3. Writeable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect S/UNIDUPLEX operation unless otherwise noted. 5. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the S/UNI-DUPLEX operates as intended, reserved register bits must only be written with logic zero. Similarly, writing to reserved registers should be avoided.
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Register 0x00: Master Reset and Identity / Load Performance Meters Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R R R R R R R Function RESET TYPE[2] TYPE[1] TYPE[0] ID[3] ID[2] ID[1] ID[0] Default 0 0 0 1 0 0 0 1
This register allows the revision number of the S/UNI-DUPLEX to be read by software permitting graceful migration to newer, feature-enhanced versions of the S/UNI-DUPLEX. In addition, writing to this register simultaneously loads all the performance meter registers in the S/UNI-DUPLEX. ID[3:0]: The ID bits can be read to provide a binary S/UNI-DUPLEX revision number. TYPE[2:0]: The TYPE bits can be read to distinguish the S/UNI-DUPLEX from the other members of the S/UNI family of devices. RESET: The RESET bit allows the S/UNI-DUPLEX to be reset under software control. If the RESET bit is a logic one, the entire S/UNI-DUPLEX is held in reset. This bit is not self-clearing. Therefore, a logic zero must be written to bring the S/UNI-DUPLEX out of reset. Holding the S/UNI-DUPLEX in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset. Otherwise, the effect of a software reset is equivalent to that of a hardware reset.
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Register 0x01: Master Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACTIVE: The ACTIVE bit reports and allows the selection of the active high-speed serial link. If ACTIVE is logic 0, the cell data and RX8K timing reference are extracted from the RXD1+/- serial link. If ACTIVE is logic 1, the cell data and RX8K timing reference are extracted from the RXD2+/- serial link. The value read reflects the link actually selected. It is either the value written if RXAUTOSEL is logic 0, or the selection based on the system prepend otherwise. The active high-speed serial link can be determined automatically depending on the value of the RXAUTOSEL bit. If RXAUTOSEL is set to logic 0, the microprocessor selects the active high-speed link by writing to the ACTIVE bit. Writing to the ACTIVE bit has no effect if the RXAUTOSEL is logic 1. RXAUTOSEL: The RXAUTOSEL bit controls the automatic selection of the active highspeed serial link. If RXAUTOSEL is logic 1, the DUPLEX switches the active link based on the status information extracted from both links. . MINTE: The Master Interrupt Enable allows internal interrupt statuses to be propagated to the interrupt output. If MINTE is logic 1, INTB will be asserted low upon the assertion of an interrupt status bit whose individual enable is set. If MINTE is logic 0, INTB is unconditionally high-impedance. Type R/W R/W R/W R/W R/W R/W R/W R/W Function Reserved Reserved LTXCINV LRXCINV RESETO MINTE RXAUTOSEL ACTIVE Default 0 0 0 0 0 0 1 0
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DUAL SERIAL LINK PHY MULTIPLEXER
RESETO: The RESETO bit controls the state of the RSTOB output. Setting RESETO to logic 1 causes the active low RSTOB output to be asserted. Setting RESETO to logic 0 causes the RSTOB output to go back to high impedance. RSTOB can also be controlled through bit oriented code received on the active highspeed link. LRXCINV: The LRXCINV bit determines the edge of the clock used to sample the LRXD[15:0] bus. When the LRXCINV bit is set to logic 1, each line of the LRXD[15:0] bus is sampled on the falling edge of the clock signal input on the corresponding LRXC[15:0] line. When the LRXCINV bit is set to logic 0, each line of the LRXD[15:0] bus is sampled on the rising edge of the clock signal input on the corresponding LRXC[15:0] line. LTXCINV: The LTXCINV bit determines the edge of the clock used to output the LTXD[15:0] bus. When the LTXCINV bit is set to logic 1, each line of the LTXD[15:0] bus is output on the falling edge of the clock signal input on the corresponding LTXC[15:0] line. When the LTXCINV bit is set to logic 0, each line of the LTXD[15:0] bus is output on the rising edge of the clock signal input on the corresponding LTXC[15:0] line. Reserved: These bits must be logic 0 for correct operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x02: Master Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX1I, RX2I: This register indicates whether there is a pending interrupt for a particular high-speed serial link receiver. RX1I is associated with RXD1+/-. and RX2I is associated with RXD2+/-. If RX1I or RX2I is logic 1, at least one interrupt status bit within the RXD1 or RXD2 High-Speed Serial Interrupt Status register that has its corresponding enable set is a logic 1. These bits are not self-clearing; they are only cleared to logic 0 by reading the RXD1 or RXD2 High-Speed Serial Interrupt Status register. TXI: This register indicates whether there is a pending interrupt for the high-speed serial link transmitter. If TXI is logic 1, the interrupt status bit in the Transmit High-Speed Serial Cell Count Status register has its corresponding enable set and is a logic 1. This bit is not self-clearing; it is only cleared to logic 0 by reading the Transmit High-Speed Serial Cell Count Status register. RFI: This register indicates whether there is a pending interrupt for the Receive Logical Channel FIFO. IF RFI is logic 1, the interrupt status bit in the Receive Logical Channel FIFO Interrupt Status register has its corresponding enable set and is a logic 1. This bit is not self-clearing; it is only cleared to logic 0 by reading the Receive Logical Channel FIFO Interrupt register. Type R R R R R R R R Function UPCIFI OCIF ICIF TFI RFI TXI RX2I RX1I Default X X X X X X X X
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
TFI: This register indicates whether there is a pending interrupt for the Transmit Logical Channel FIFO. If TFI is logic 1, the interrupt status bit in the Transmit Logical Channel FIFO Interrupt Status register has its corresponding enable set and is a logic 1. This bit is not self-clearing; it is only cleared to logic 0 by reading the Transmit Logical Channel FIFO Interrupt Status register. ICIFI This register indicates whether there is a pending interrupt for the SCIPHY/Any-PHY interface input port. If ICIFI is logic 1, at least one interrupt status bit within the SCI-PHY/Any-PHY Input Interrupt Status register that has its corresponding enable set is a logic 1. This bit is not self-clearing; it is only cleared to logic 0 by reading the SCIPHY/Any-PHY Input Interrupt Status register. OCIFI This register indicates whether there is a pending interrupt for the SCIPHY/Any-PHY Interface output port. If OCIFI is logic 1, at least one interrupt status bit within the SCI-PHY/Any-PHY Output Configuration and Interrupt Status register that has its corresponding enable set is a logic 1. This bit is not self-clearing; it is only cleared to logic 0 by reading the SCIPHY/Any-PHY Output Configuration and Interrupt Status register UPCIFI: This bit indicates whether there is a pending interrupt for the Microprocessor Cell Interface. If UPCIFI is logic 1, at least one interrupt status bit within the Microprocessor Cell Buffer Interrupt register that has its corresponding enable set is a logic 1. This bit is not self-clearing; it is only cleared to logic 0 by reading the Microprocessor Cell Buffer Interrupt register.
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x03: Miscellaneous Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROOLI: The Reference Out of Lock interrupt (ROOLI) status is a logic 1 if the ROOLV bit of the Clock Monitor register has changed state since the last time this register was read. The ROOLI bit is reset when this register is read. RBOCI This bit indicates whether there is a pending interrupt for the RXD1, RXD2 Bit Oriented Code Status registers. If RBOCI is logic 1, at least one interrupt status bit within the RXD1 Receive Bit Oriented Code Status register or the RXD2 Bit Oriented Code Status register that has its corresponding enable set is a logic 1. RCSDI: This register indicates whether there is a pending interrupt for the receive Clocked Serial Data Interface. If RCSDI is logic 1, at least one interrupt status bit within one of the Receive Serial Indirect Channel Interrupt and Status register that has its corresponding enable set is a logic 1. This bit is cleared upon a read of this register. UPFI: This bit indicates whether there is a pending interrupt for one of the Microprocessor Extract FIFOs. If UPFI is logic 1, at least one interrupt status bit within the Microprocessor RXD1 FIFO Interrupt Status register or Microprocessor RXD2 FIFO Interrupt Status register that has its corresponding enable set is a logic 1. R R R R Type Function Unused Unused Unused Unused UPFI RCSDI RBOCI ROOLI Default X X X X X X X X
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DUAL SERIAL LINK PHY MULTIPLEXER
This bit is not self-clearing; it is only cleared to logic 0 by reading the RXD1 Extract FIFO Interrupt Status register or the Microprocessor RXD2 Extract FIFO Interrupt Status register.
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x04: Clock Monitor Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R R R R Type Function Unused Unused Unused ROOLE ROOLV REFCLKA OFCLKA IFCLKA Default X X X 0 X X X X
This register provides activity monitoring of the S/UNI-DUPLEX clocks. When a monitored clock signal makes a low to high transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point, all the bits in this register are cleared. A lack of transitions is indicated by the corresponding register bit reading low. This register should be read at periodic intervals to detect clock failures. The register also reports the state of the clock synthesis unit that generates the internal clocks. IFCLKA: The IFCLK active (IFCLKA) bit monitors for low to high transitions on the IFCLK SCI-PHY/Any-PHY interface clock input. IFCLKA is set high on a rising edge of IFCLK, and is set low when this register is read. When the Clocked Serial Data interface is used (SCIANY input tied to logic 0), the IFCLKA bit monitors the internally generated CSDCLK. This clock is generated by dividing the high-speed serial link clock by 6. OFCLKA: The OFCLK active (OFCLKA) bit monitors for low to high transitions on the OFCLK SCI-PHY/Any-PHY interface clock input. OFCLKA is set high on a rising edge of OFCLK, and is set low when this register is read. When the Clocked Serial Data interface is used (SCIANY input tied to logic 0), the IFCLKA bit monitors the internally generated CSDCLK. This clock is generated by dividing the high-speed serial link clock by 6.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
REFCLKA: The REFCLK active (REFCLKA) bit monitors for low to high transitions on the REFCLK reference clock input. REFCLKA is set high on a rising edge of REFCLK, and is set low when this register is read. ROOLV: The reference out of lock status indicates the clock synthesis phase locked loop is unable to lock to the reference on REFCLK. ROOLV is a logic one if the synthesized clock frequency is not within 488 ppm of eight times the REFCLK frequency. ROOLE: The ROOLE bit is an interrupt enable for the transmit reference out of lock status. When ROOLE and the Master Interrupt Enable bit of the Master Configuration register are set to logic one, the INTB output is asserted low when the ROOLV bit changes state.
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x05: Serial Links Maintenance Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DLB1: The Diagnostic Loopback 1 enable bit allows TXD1+/- data to replace RXD1+/- data. When DLB1 is logic 1, the receive circuitry for the serial link is timed off the internal transmit clock and the TXD1+/- data is multiplexed into RXD1+/- just after the clock recovery. Upstream data is effectively routed to the downstream datapath if the corresponding high-speed serial link is active. DLB2: The Diagnostic Loopback 2 enable bit allows TXD2+/- data to replace RXD2+/- data. When DLB2 is logic 1, the receive circuitry for the serial link is timed off the internal transmit clock and the TXD2+/- data is multiplexed into RXD2+/- just after the clock recovery. Upstream data is effectively routed to the downstream datapath if the corresponding high-speed serial link is active. MLB1: The Metallic Loopback 1 enable bit allows RXD1+/- data to be presented on TXD1+/-. When LLB is logic one, the sliced receive data replaces the transmit data at the high-speed transmitter. Note that the loopback can also be activated remotely through inband bit oriented codes. MLB2: The Metallic Loopback 2 enable bit allows RXD1+/- data to be presented on TXD1+/-. When LLB is logic one, the sliced receive data replaces the transmit data at the high-speed transmitter. Type R/W R/W R/W R/W R/W R/W R/W R/W Function RDIDIS2 RDIDIS1 TXDIS2 TXDIS1 MLB2 MLB1 DLB2 DLB1 Default 0 0 0 0 0 0 0 0
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DUAL SERIAL LINK PHY MULTIPLEXER
Note that the loopback can also be activated remotely through inband bit oriented codes. TXDIS1: The Transmit Disable 1 bit disables the high-speed outputs. If TXDIS1 is logic one, the TXD1+/- outputs do not drive valid logic levels, but instead float. TXDIS does not affect the differential output impedance; it is always within the range specified in the D.C. Characteristics section.. TXDIS2: The Transmit Disable 2 bit disables the high-speed outputs. If TXDIS2 is logic one, the TXD2+/- outputs do not drive valid logic levels, but instead float. TXDIS does not affect the differential output impedance; it is always within the range specified in the D.C. Characteristics section. RDIDIS1: The RDI Disable 1 bit disables the automatic transmission of a RDI codeword on TXD1+/-. If RDIDIS1 is logic zero, the declaration of LOS or LCD results in the RDI codeword being transmitted in the BOC bit position . Note that RDI can be sent manually by writing all zeros to the TXD1 Transmit Bit Oriented Code register. RDIDIS2: The RDI Disable 2 bit disables the automatic transmission of a RDI codeword on TXD2+/-. If RDIDIS2 is logic zero, the declaration of LOS or LCD results in the RDI codeword being transmitted in the BOC bit position . Note that RDI can be sent manually by writing all zeros to the TXD2 Transmit Bit Oriented Code register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x06: Extended Address Match (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XAD[7:0] This register in conjunction with the XAD[10:8]bits of the Extended Address Match (MSB) register is used in the selection of the SCI-PHY/Any-PHY input port for cell transfer when operating in Any-PHY bus slave mode (ANYPHY input set to logic 1, IMASTER input set to logic 0). Cells are accepted if the value in the Extended Address field of the prepend is equal with the XAD[10:0] bits over the range of bits specified by the Extended Address Mask registers. When operating the SCI-PHY/Any-PHY output port in bus slave (OMASTER input set to logic 0), the XAD[2:0] bits are inserted in the three most significant bits of the Extended Address field of the prepend in the eight bit format and the XAD[11:0] bits are inserted in the 11 most significant bits of the Extended Address field of the prepend in 16 bit format. Type R/W R/W R/W R/W R/W R/W R/W R/W Function XAD[7] XAD[6] XAD[5] XAD[4] XAD[3] XAD[2] XAD[1] XAD[0] Default 0 0 0 0 0 0 0 0
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x07: Extended Address Match (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XAD[10:8]] These are the three most significant bits of the Extended Address Match. R/W R/W R/W Type Function Unused Unused Unused Unused Unused XAD[10] XAD[9] XAD[8] Default X X X X X 0 0 0
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x08: Extended Address Mask (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XAM[7:0] The XAM[7:0] bits are used in conjunction with the XAM[10:8] bits of the Extended Address Mask (MSB) register to mask bits of the Extended Address Match registers when comparing it with the Extended Address field of the prepend. When a bit of XAM[10:0] is set to logic 0, the corresponding bit of the Extended Address Match registers is masked in the comparison process. i.e. a match occurs independently of the Extended Address Match bit value. Type R/W R/W R/W R/W R/W R/W R/W R/W Function XAM[7] XAM[6] XAM[5] XAM[4] XAM[3] XAM[2] XAM[1] XAM[0] Default 0 0 0 0 0 0 0 0
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x09: Extended Address Mask (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XAM[10:8]] These are the three most significant bits of the Extended Address Match. R/W R/W R/W Type Function Unused Unused Unused Unused Unused XAM[10] XAM[9] XAM[8] Default X X X X X 0 0 0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x0A: Output Address Match Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OAD[4:0] The OAD[4:0] bits are used in the selection of the output port of the SCIPHY/Any-PHY interface for polling and cell transfer. Polling occurs when the OAVALID input is sampled high and the sampled OADDR[4:0] inputs match the OAD[4:0] bits. A transfer is enacted if the value of the OADDR[4:0] inputs equals the OAD[4:0] bits when OENB is last sampled high. OCAEN: The OCAEN bit controls whether the OCA output is driven in response to polling when the SCI-PHY/Any-PHY interface output port is operated in bus slave mode (OMASTER set to logic 0). If OCAEN is set to logic 0, the OCA output pin stays unconditionally high impedance. If OCAEN is set to logic 1, OCA drives upon sampling a logic 1 on OAVALID while OADDR[4:0] value is equal to OAD[4:0] bits of this register. OCAEN should only be set to logic 1 after the aforementioned register bits have been initialized. R/W R/W R/W R/W R/W R/W Type Function Unused Unused OCAEN OAD[4] OAD[3] OAD[2] OAD[1] OAD[0] Default X X 0 0 0 0 0 0
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DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x0B: Configuration Pins Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R Type Function Unused SCIANYV OBUS8V OANYPHYV OMASTERV IBUS8V IANYPHYV IMASTERV Default X X X X X X X X
The Configuration Pins Status Register reflects the value of the S/UNI-DUPLEX input pins used to configure the Clocked Serial Data and the SCI-PHY/Any-PHY interfaces. The IMASTERV, IANYPHYV, IBUS8V, OMASTERV, OANYPHYV, OBUS8V values are only meaningful when the SCIANY pin is high. IMASTERV: When IMASTERV is high, the SCI-PHY/Any-PHY interface input port is configured as a bus master. When IMASTERV is low the, input port is configured as a bus slave. IANYPHYV: When IANYPHYV is high, the SCI-PHY/Any-PHY interface input port complies with the Any-PHY protocol. When IANYPHYV is low the, input port complies with the SCI-PHY/Utopia protocol. IBUS8V: When IBUS8V is high, the SCI-PHY/Any-PHY interface input port is eight bit wide. When IBUS8V is low, the SCI-PHY/Any-PHY interface input port is sixteen bit wide. OMASTERV: When OMASTERV is high, the SCI-PHY/Any-PHY interface output port is configured as a bus master. When OMASTERV is low the, input port is configured as a bus slave.
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DUAL SERIAL LINK PHY MULTIPLEXER
OANYPHYV: When OANYPHYV is high, the SCI-PHY/Any-PHY interface output port complies to the Any-PHY protocol. When OANYPHYV is low the, output port complies to the SCI-PHY/Utopia protocol. OBUS8V: When OBUS8V is high, the SCI-PHY/Any-PHY interface output port is eight bit wide. When OBUS8V is low, the SCI-PHY/Any-PHY interface output port is sixteen bit wide. SCIANYV: When SCIANYV is high, the SCI-PHY/Any-PHY interface is used to exchange cells with the DUPLEX. When SCIANYV is low, the Clocked Serial Data interface is used to exchange cells with the DUPLEX.
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x0C: SCI-PHY/Any-PHY Input Configuration 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTYP: The Parity Type (PTYP) bit selects even or odd parity for the IPRTY input of the SCI-PHY/Any-PHY input port. When set to logic 1, IPRTY is the even parity bit for IDAT[15:0] if IBUS8 input is low or for IDAT[7:0] if IBUS8 input is high. When set to logic 0, IPRTY is the odd parity bit for IDAT[15:0] if IBUS8 input is low or for IDAT[7:0] if IBUS8 input is high. PRELEN[1:0]: The Prepend Length (PRELEN[1:0]) bits determine the number of words prepended to each cell received on the SCI-PHY/Any-PHY input port. When IBUS8 is a logic 1, the binary PRELEN[1:0] value indicates whether the optional "Word 1" and "Word 2" illustrated in Fig. 6 are included in the data structure expected on IDAT[7:0]. The possible values are: PRELEN[1:0] 00 01 10 Description no prepended word "Word 1" only is included "Word 1:" and "Word 2" are included R/W R/W R/W R/W Type R/W Function H5UDF Unused Unused Reserved PRELEN[1] PRELEN[0] Unused PTYP Default 1 X X 0 0 0 X 0
When IBUS8 is a logic 0, only PRELEN[0] is used. When PRELEN[0] is logic 1, the optional "Word 1" illustrated in Fig. 7 is included in the data structure expected on IDAT[15:0]. Reserved: This bit must be logic 0 for correct operation.
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H5UDF: The H5UDF bit determines whether or not the H5/UDF octets are included in cells transferred over the SCI-PHY/Any-PHY input port. When H5UDF is set to logic 1 (default), the H5 and UDF octets are included, i.e. the optional "Word 4" illustrated in Fig. 6 and Fig. 7 is included in the 8-bit or 16-bit data structure expected on IDAT[15:0].
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DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x0D: SCI-PHY/Any-PHY Input Configuration 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused ENFLTR NNI PHYDEV[4] PHYDEV[3] PHYDEV[2] PHYDEV[1] PHYDEV[0] Default X 0 1 0 0 0 0 0
PHYDEV[4:0]: The PHYDEV[4:0] bits are used to define the polling range of the SCIPHY/Any-PHY input port when configured as a bus master (IMASTER is set to logic 1) The number of PHY devices to be polled is configured as follows: PHYDEV[4:0] 00000 00001 00010 00011 : 11110 11111 Description Poll all 32 devices Poll PHY#1 thru PHY#2 Poll PHY#1 thru PHY#3 Poll PHY#1 thru PHY#4 : Poll PHY#1 thru PHY#31 Poll all 32 PHY devices
Setting PHYDEV[4:0] to poll more PHY devices than actually connected to the SCI-PHY/Any-PHY input port may result in loss of cell throughput due to longer than necessary polling cycles. NNI: The NNI bit selects whether the UNI or NNI cell header format is used when determining whether a cell is unassigned or reserved for the Physical Layer. When set to logic 1 (default), the NNI format is used. When set to logic 0, the UNI format is used, i.e. the 4 most significant bits of Byte 1 of the cell header are ignored.
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ENFLTR: The ENFLTR bit controls the transfer of Physical Layer and unassigned cells over the SCI-PHY/Any-PHY input port. If ENFLTR is set logic 1, Physical Layer and unassigned cells are removed from the cells transferred over the SCI-PHY/Any-PHY input port. If ENFLTR is set logic 0, all cells, including Physical Layer and unassigned cells are transferred over the SCI-PHY/AnyPHY input port.
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DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x0E: SCI-PHY/Any-PHY Input Interrupt Enables Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W Type Function Unused Unused Unused Unused Unused PHYCELLE CELLXFERRE PARERRE Default X X X X X 0 0 0
The Master Interrupt Enable bit of the Master Configuration register must also be logic 1 for these enables to take effect. PHYCELLE: The PHYCELLE bit enables the generation of an interrupt when a physical layer cell is transferred over the SCI-PHY/Any-PHY input port. When PHYCELLE is set to logic 1, the interrupt is enabled. Physical layer cells are defined in the I.361 standard as IDLE, unassigned and reserved cells (i.e. cells with a VPI = 0 and VCI = 0). These cells should be filtered out by the PHY device and would not normally be sent to the S/UNI-DUPLEX. CELLXFERRE: The CELLXFERRE bit enables the generation of an interrupt upon an invalid start of cell sequence. When CELLXFERRE is set to logic 1, the interrupt is enabled. PARERRE: The PARRERRE bit enables the generation of an interrupt on an input cell parity error. When PARRERE is set to logic 1, the interrupt is enabled.
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DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x0F: SCI-PHY/Any-PHY Input Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PHYCELLI: The PHYCELLI bit is set to logic 1 when a physical cell is transferred over the SCI-PHY/Any-PHY input port. This bit is reset immediately after a read to this register. CELLXFERRI: The CELLXFERRI bit is set to logic 1 when an invalid start of cell sequence is detected, i.e. ISOC or ISX is asserted when not expected at the SCIPHY/Any-PHY input port. This bit is reset immediately after a read to this register. The same event that asserts this bit may also result in a corrupted cell being transmitted on a high-speed serial link. PARERRI: The PARERRI bit is set to logic 1 when a parity error occurs while receiving a cell at the SCI-PHY/Any-PHY input port. This bit is reset immediately after a read to this register. R R R Type Function Unused Unused Unused Unused Unused PHYCELLI CELLXFERRI PARERRI Default X X X X X 0 0 0
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DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x10: Input Cell Available Enable (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function ICAEN[7] ICAEN[6] ICAEN[5] ICAEN[4] ICAEN[3] ICAEN[2] ICAEN[1] ICAEN[0] Default 1 1 1 1 1 1 1 1
Register 0x11: Input Cell Available Enable (2nd) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function ICAEN[15] ICAEN[14] ICAEN[13] ICAEN[12] ICAEN[11] ICAEN[10] ICAEN[9] ICAEN[8] Default 1 1 1 1 1 1 1 1
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Register 0x12: Input Cell Available Enable (3rd) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function ICAEN[23] ICAEN[22] ICAEN[21] ICAEN[20] ICAEN[19] ICAEN[18] ICAEN[17] ICAEN[16] Default 1 1 1 1 1 1 1 1
Register 0x13: Input Cell Available Enable (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICAEN[31:0]: The four registers of ICAEN[31:0] control the polling of devices attached to the SCI-PHY/Any-PHY input port. When operating in master mode (IMASTER input set to logic 1), the ICAEN[31:0] bits can be used to selectively remove a PHY device from the polling sequence. Setting a bit of ICAEN[31:0] to logic 0 prevents the S/UNIDUPLEX to poll the corresponding device. When operating in slave mode, the ICAEN[31:0] bits can be used to disable logical channels. Logical channels are disabled in group of four consecutive addresses, i.e. setting to logic 0 one or more bits of a four bit nibble of ICA[31:0] disables all four corresponding logical channels. If a disabled PHY Type R/W R/W R/W R/W R/W R/W R/W R/W Function ICAEN[31] ICAEN[30] ICAEN[29] ICAEN[28] ICAEN[27] ICAEN[26] ICAEN[25] ICAEN[24] Default 1 1 1 1 1 1 1 1
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address is polled, ICA remains high impedance. Similarly, PHY selection is ignored and no cells are transferred to the S/UNI-DUPLEX when a disabled PHY is addressed. This is typically used to allow more than one slave device to share the cell input bus. Disabling all traffic to the SCIPHY/Any-PHY input port is achieved by setting all ICAEN[31:0] bits to logic 0. Setting the Input Cell Available registers to other values than the default value may cause the device to behave erratically when the S/UNI-DUPLEX is configured for Clocked Serial Data interface (SCIANY input is low).
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Register 0x14: SCI-PHY/Any-PHY Output Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTYP: The Parity Type (PTYP) bit selects even or odd parity for the OPRTY output of the SCI-PHY output port. When set to logic 1, OPRTY completes even parity bit for ODAT[15:0] if OBUS8 input is low or for ODAT[7:0] if OBUS8 input is high. When set to logic 0, OPRTY completes odd parity bits for ODAT[15:0] if OBUS8 input is low or for ODAT[7:0] if OBUS8 input is high. PRELEN[1:0]: The Prepend Length (PRELEN[1:0]) bits determine the number of prepended words to each cell When OBUS8 is a logic 1, the binary PRELEN[1:0] value indicates whether the optional "Word 1" and "Word 2" illustrated in Fig. 6 are included in the data structure presented on ODAT[7:0]. The possible values are: PRELEN[1:0] 00 01 10 Description no prepended word "Word 1" only is included "Word 1:" and "Word2" are included R/W R/W R/W R/W R/W Type R R/W Function CELLXFERRI CELLXFERRE Unused INADDUDF H5UDF PRELEN[1] PRELEN[0] PTYP Default X 0 X 0 1 0 0 0
When OBUS8 is a logic 0, only PRELEN[0] is used. When PRELEN[0] is logic 1, the optional "Word 1" illustrated in Fig. 7 is included in the data structure presented on ODAT[15:0]. H5UDF: The H5UDF bit determines whether or not the H5/UDF octets are included in cells transferred over the SCI-PHY/Any-PHY output port. When H5UDF is set
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to logic 1 (default) and the eight bit SCI-PHY/Any-PHY cell format is used (OBUS8 input set to logic 1), the H5 byte is included, i.e. the optional "Word 7" illustrated in Fig. 6, in the data structure expected on ODAT[7:0]. When H5UDF is set to logic 1 (default) and the 16 bit SCI-PHY/Utopia/Any-PHY cell format is used (OBUS8 input set to logic 0), the H5 and UDF octets are included, i.e. the optional "Word 4" illustrated in Fig. 7, in the data structure expected on ODAT[15:0]. INADDUDF: The INADDUDF bit relocates the word identifying the logical channel in the H5/UDF field when the output port is configured as a SCI-PHY/Utopia bus slave. When this bit is set to logic 1 and eight bit cell format is used (OBUS8 input set to logic 1), the logical channel is identified in the five lower bits of the H5 byte. The three upper bits of the H5 register are set to the value of the three least significant bits of the Extended Address Match register, which default to all zeros. When this bit is set to logic 1 and 16 bit cell format is used (OBUS8 input set to logic 0), the logical channel is identified in the five lower bits of the H5/UDF word. The eleven remainder bits of the H5/UDF word are set to the value of the Extended Address Match register, which default to all zeros. In both cases, "Word 0" is excluded from the cell data (refer to Fig. 6 and Fig. 7). For proper operation to occur when INADDUDF is set to 1 the H5UDF bit must also be set to one (its default value). This bit has no effect when the SCI-PHY/Any-PHY Output port is not configured as a SCI-PHY/Utopia bus slave. CELLXFERRE: The Cell Transfer Error Interrupt Enable (CELLXFERRE) bit allows the generation of an interrupt on an invalid selection by an external master device. This occurs when a cell transfer is attempted, but the S/UNI-DUPLEX has indicated no cell is available by returning OCA low when polled. When CELLXFERRE is set to logic 1, the INTB output is asserted low when the CELLXFERRI bit is logic 1. CELLXFERRI: The CELLXFERRI bit provides a status of the Cell Transfer Error Interrupt. The CELLXFERRI is only valid when the SCI-PHY/Any-PHY Interface output port is configured as a bus slave (OMASTER=low). This interrupt status is asserted upon the selection by the external bus master of the SCI-PHY/AnyPHY Interface output port for a transfer without a cell being available, i.e. the S/UNI-DUPLEX has indicated no cell is available by returning OCA low when polled. The CELLXFERRI bit will not be asserted when the OENB is maintained low beyong the end of a cell transfer even if no new cell is
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available. This bit is reset immediately after a read to this register.
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Register 0x15: SCI-PHY/Any-PHY Output Polling Range Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Type Function Unused Unused Unused PHYDEV[4] PHYDEV[3] PHYDEV[2] PHYDEV[1] PHYDEV[0] Default X X X 0 0 0 0 0
PHYDEV[4:0]: The PHYDEV[4:0] bits are used to define the polling range of the SCIPHY/Any-PHY output port when configured as a bus master (OMASTER is set to logic 1). The number of PHY devices to be polled is configured as follows: PHYDEV[4:0] 00000 00001 00010 00011 : 11110 11111 Description Poll all 32 devices Poll PHY#1 thru PHY#2 Poll PHY#1 thru PHY#3 Poll PHY#1 thru PHY#4 : Poll PHY#1 thru PHY#31 Poll all 32 PHY devices
Setting PHYDEV[4:0] to poll more PHY devices than actually connected to the SCI-PHY/Any-PHY output port may result in loss of cell throughput due to longer than necessary polling cycles
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Registers 0x18, 0x1A: RXD1, RXD2 Bit Oriented Code Receiver Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W Type Function Unused Unused Unused Unused Unused IDLE AVC BOCE Default X X X X X 0 0 0
These registers select the validation criteria to be used in determining a valid bit oriented code (BOC) and enables generation of an interrupt on a change in code status of the BOC received on RXD1+/- and RXD2+/-. IDLE: The IDLE bit enables the assertion of the INTB output when there is a transition from a validated BOC to idle code. When IDLE and the Master Interrupt Enable bit of the Master Configuration register are set to logic 1, the interrupt is enabled. AVC: The AVC bit position selects the validation criteria used in determining a valid BOC. A logic 1 in the AVC bit position selects an alternate validation criterion of 4 out of 5 matching BOCs; a logic 0 selects the 8 out of 10 matching BOC criterion. Unless fast declaration is necessary, it is recommended that AVC be set to logic 0 to improve bit error tolerance. BOCE: The BOCE bit enables the assertion of the INTB output when a valid BOC is detected. When BOCE and the Master Interrupt Enable bit of the Master Configuration register are set to logic 1, the interrupt is enabled.
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Register 0x19, 0x1B: RXD1, RXD2 Receive Bit Oriented Code Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BOC[5:0]: The BOC[5:0] bits indicate the current state value of the received bit-oriented code. The value is updated when the BOC has been a valid code 8 out of 10 or 4 out of 5 times, as selected by the AVC bit of the Bit Oriented Code Receiver Enable register. These bits are set to all ones (111111) if no valid code has been detected. An update is accompanied by a logic 1 in the BOCI bit. IDLEI: The IDLEI bit position indicates the detection of a transition from a valid BOC to idle or invalidated state code value of 111111. A logic 1 in the IDLEI bit position indicates that a transition from a valid BOC to idle or invalid code has generated an interrupt; a logic 0 in the IDLEI bit position indicates that no transition from a valid BOC to idle code has been detected. IDLEI will also set when no code is currently validated. Note that failure to meet the 8 of 10 (or 4 of 5) persistency criteria, either due to bit errors or a change to a new code, does result in IDLEI being set. IDLEI is cleared to logic 0 when the register is read. BOCI: The BOCI bit position indicates the detection of a valid BOC. BOCI becomes logic 1 when BOC[5:0] changes from the transition or IDLE code value of 111111. BOCI is cleared to logic 0 when the register is read. BOCI will not be set at the transition to a validated IDLE code. Type R R R R R R R R Function IDLEI BOCI BOC[5] BOC[4] BOC[3] BOC[2] BOC[1] BOC[0] Default X X X X X X X X
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Registers 0x1D, 0x1F: TXD1, TXD2 Transmit Bit Oriented Code Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W Type Function Unused Unused BC[5] BC[4] BC[3] BC[2] BC[1] BC[0] Default X X 1 1 1 1 1 1
This register enables the generation of a bit oriented code and selects the 6-bit code to be transmitted in the BOC bit position of the corresponding TXD1+/-.or TXd2+/- high-speed serial link. The contents of the register will be transmitted repeatedly in the BOC bit position of the corresponding TXD1+/- or TXD2+/- high-speed serial link with the format 111111110[BC0][BC1][BC2][BC3][BC4][BC5]0, provided a Remote Defect Indication (RDI) is not currently being transmitted. The default value represents an idle code.
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Register 0x20: Microprocessor Cell Buffer Interrupt Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R/W R/W R/W R/W Function EXTCRCERRI EXTRDYI INSOVRI INSRDYI EXTCRCERRE EXTRDYE INSOVRE INSRDYE Default X X X X 0 0 0 0
The Master Interrupt Enable bit of the Master Configuration register must also be logic 1 for the interrupt enables to take effect. INSRDYE: The INSRDYE bit allows the generation of an interrupt signal when the Insert FIFO becomes available. When INSRDYE is set to logic 1, the INTB output is asserted low when the INSRDYI bit is logic 1. INSOVRE: The INSOVRE bit controls the generation an interrupt signal when a write access is done to a full Insert FIFO. When INSOVRE is set to logic 1, the INTB output is asserted low when the INSOVRI bit is logic 1. EXTRDYE: The EXTRDYE bit allows the generation of an interrupt signal when an Extract FIFO becomes ready. When EXTRDYE is set to logic 1, the INTB output is asserted low when the EXTRDYI bit is logic 1. EXTCRCERRE: The EXTCRCERRE bit controls the generation an interrupt signal upon detection of a CRC-32 error at the end of a cell read access. When EXCRCERRE is set to logic 1, the INTB output is asserted low when the EXTCRCERRI bit is logic 1.
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INSRDYI: The INSRDYI bit provides the status of the Insert FIFO Ready Interrupt. This bit is set to logic 1 when the Insert FIFO becomes ready to accept a cell (i.e. a cell is transferred from a full FIFO) or upon the completion of a cell write if at least one more cell can be written. Ready status of a specific FIFO is indicated by a logic 1 at the corresponding bit of the Microprocessor Insert FIFO Ready register. The INSRDYI bit is reset immediately after a read to this register. INSOVRI: The INSOVRI bit indicates the status of the write access to the Insert FIFO. This bit is set to high when a write access has being done to a full Insert FIFO and that the data has been discarded. This bit is reset immediately after a read to this register. EXTRDYI: The EXTRDYI bit provides the status of the Extract FIFOs Ready Interrupt. This bit is set to logic 1 when one of the Extract FIFO becomes ready for a cell read (i.e. upon reception of the only cell in the FIFO) or upon the completion of a cell read if there is at least one more cell to be read from the FIFO. Ready status of a specific FIFO is indicated by a logic 1 at the corresponding bit of the Microprocessor Insert FIFO Ready register. This bit is reset immediately after a read to this register. EXTCRCERRI: The EXTCRCERRI bit indicates the CRC-32 status of a cell read from an Extract FIFO. When the EXTCRCCHK bit is set to logic 1, the EXTCRCERRI bit is updated when the last byte of a cell is read by the microprocessor. It is set to logic 1 if the value of the Extract CRC Accumulator register differs from the expected CRC-32 remainder polynomial. Otherwise, it is set to logic 0. This bit is also reset immediately after a read to this register.
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Register 0x21: Microprocessor Insert FIFO Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INSRST: The INSRST bit allows the microprocessor to abort a cell write to the Insert FIFO. If INSRST is set to a logic 1 when previously logic 0, the extract pointer is reset without completing the transaction. Setting INSRST after the last write (i.e. at the beginning of the next cell) has no effect. To abort a cell, the microprocessor must have written at least the first byte of the cell but less than 56 bytes. INSRST is not readable. This bit is cleared on every write to Microprocessor Cell Data register. INSCRCPR: The INSCRCPR bit is used to force the value of the Insert CRC-32 accumulation register to its preset value. If INSCRCPR is set to logic 1, the Insert CRC-32 accumulation register is kept to its preset value. If INSCRCPR is set to logic 0, CRC-32 calculations are performed on inserted cells. CRC32 calculations are performed on the cell payload bytes being written to the Microprocessor Cell Data register. INSCRCEND: The INSCRCEND bit is used to indicate that the following inserted cell is the last one of the CPCS-PDU. Setting this bit to logic 1 will cause the last four bytes of the cell transferred from the microprocessor to be replaced by the value of the ones complement of the Insert CRC-32 Accumulation register. R/W R/W W Type Function Unused Unused INSCRCEND INSCRCPR INSRST Unused Unused Unused Default X X 0 1 X X X X
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Register 0x22: Microprocessor Extract FIFO Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXTFSEL: The EXTFSEL bit is used to select the one of Microprocessor Extract FIFOs for a cell read operation. A logic 0 in EXTFSEL selects the Extract FIFO associated with RXD1+/-. A logic 1 in EXTFSEL selects the Extract FIFO associated with RXD2+/-. The Extract FIFO has to be selected prior to starting the cell transfer. Due to synchronization delays, a read of the Microprocessor Cell Buffer Data register should not be initiated until two REFCLK periods after completion of the write of these bits. EXTABRT: The EXTABRT bit allows the microprocessor to discard a cell without reading the remaining contents. If EXTABRT is set to a logic 1 when previously logic 0, the extract pointer is reset, effectively discarding the remaining content of the cell. Setting EXTABRT after the last read (i.e. at the beginning of the next cell) has no effect. To abort a cell, the microprocessor must have read at least the first word of the cell but no more than 56 bytes. Due to synchronization delays, no cell extraction operation should be initiated until two REFCLK periods after completion of the write of this bit. EXTABRT is not readable. It is cleared on every read from normal mode Microprocessor Cell Data register. R/W R/W R/W W Type Function Unused Unused EXTCRCCHK EXTCRCPR EXTABRT Unused Unused EXTFSEL Default X X 0 1 X X X 0
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EXTCRCPR: The EXTCRCPR bit is used to force the value of the Extract CRC-32 accumulation register to its preset value. If EXTCRCPR is set to logic 1, the Insert CRC-32 accumulation register is kept to its preset value. If EXTCRCPR is set to logic 0, CRC-32 verification is performed on extracted cells. The CRC-32 calculations are performed on the bytes being read from the location of the Microprocessor Cell Data register corresponding to the payload of extract cells. Due to synchronization delays, a read of the Microprocessor Cell Buffer Data register should not be initiated until two REFCLK periods after completion of the write of this bit. EXTCRCCHK: The EXTCRCCHK bit is used to enable the CRC-32 field check. Setting this bit to logic 1 will cause the S/UNI-DUPLEX to verify if the value of the Extract CRC-32 Accumulation register is equal to the expected CRC-32 remainder polynomial at the end of a cell read access by the microprocessor. If EXTCRCCHK is logic 1, the EXTCRCERRI bit will be set to logic 1 if the CRC-32 value is incorrect.
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Register 0x23: Microprocessor Insert FIFO Ready Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INSRDY The INSRDY bit provides the ready status of the Microprocessor Insert FIFO. A logic 1 in the INSRDY bit indicates that the Microprocessor Insert FIFO is ready to accept a cell. Note that the INSRDY bit will always return a logic 0 if the FIFO is currently being written to. R Type Function Unused Unused Unused Unused Unused Unused Unused INSRDY Default X X X X X X X X
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Register 0x24: Microprocessor Extract FIFO Ready Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXTRDY[1:0]: The EXTRDY[1:0] bits provide the ready status of the Extract FIFOs. A logic 1 in a EXTRDY[0] bit indicates that the Extract FIFO associated with RXD1+/as at least one cell available for reading. A logic 1 in a EXTRDY[1] bit indicates that the Extract FIFO associated with RXD2+/- as at least one cell available for reading. Note that the EXTRDY bit for the FIFO currently being read will always return a logic 0. R R Type Function Unused Unused Unused Unused Unused Unused EXTRDY[1] EXTRDY[0] Default X X X X X X X X
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Register 0x25: Insert CRC-32 Accumulator (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function INSCRCACC[7] INSCRCACC[6] INSCRCACC[5] INSCRCACC[4] INSCRCACC[3] INSCRCACC[2] INSCRCACC[1] INSCRCACC[0] Default 1 1 1 1 1 1 1 1
Register 0x26: Insert CRC-32 Accumulator (2nd) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function INSCRCACC[15 ] INSCRCACC[14 ] INSCRCACC[13 ] INSCRCACC[12 ] INSCRCACC[11] INSCRCACC[10 ] INSCRCACC[9] INSCRCACC[8] Default 1 1 1 1 1 1 1 1
Register 0x27: Insert CRC-32 Accumulator (3rd) Bit Bit 7 Type R/W Function INSCRCACC[23 ] Default 1
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Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type R/W R/W R/W R/W R/W R/W R/W
Function INSCRCACC[22 ] INSCRCACC[21 ] INSCRCACC[20 ] INSCRCACC[19 ] INSCRCACC[18 ] INSCRCACC[17 ] INSCRCACC[16 ]
Default 1 1 1 1 1 1 1
Register 0x28: Insert CRC-32 Accumulator (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function INSCRCACC[31] INSCRCACC[30] INSCRCACC[29] INSCRCACC[28] INSCRCACC[27] INSCRCACC[26] INSCRCACC[25] INSCRCACC[24] Default 1 1 1 1 1 1 1 1
INSCRCACC[31:0]: The four registers of INSCRCACC[31:0] allow the microprocessor to read or write the contents of the Insert CRC Accumulator register. This register accumulates the CRC-32 value over the data being written to the Insert FIFO. The rising edge of WRB for two successive write accesses to these registers must separated by at least three REFCLK periods.
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Register 0x29: Extract CRC-32 Accumulator (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function EXTCRCACC[7] EXTCRCACC[6] EXTCRCACC[5] EXTCRCACC[4] EXTCRCACC[3] EXTCRCACC[2] EXTCRCACC[1] EXTCRCACC[0] Default 1 1 1 1 1 1 1 1
Register 0x2A: Extract CRC-32 Accumulator (2nd) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function EXTCRCACC[15] EXTCRCACC[14] EXTCRCACC[13] EXTCRCACC[12] EXTCRCACC[11] EXTCRCACC[10] EXTCRCACC[9] EXTCRCACC[8] Default 1 1 1 1 1 1 1 1
Register 0x2B: Extract CRC-32 Accumulator (3rd) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Type R/W R/W R/W R/W R/W Function EXTCRCACC[23] EXTCRCACC[22] EXTCRCACC[21] EXTCRCACC[20] EXTCRCACC[19] Default 1 1 1 1 1
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Bit Bit 2 Bit 1 Bit 0
Type R/W R/W R/W
Function EXTCRCACC[18] EXTCRCACC[17] EXTCRCACC[16]
Default 1 1 1
Register 0x2C: Extract CRC-32 Accumulator (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function EXTCRCACC[31] EXTCRCACC[30] EXTCRCACC[29] EXTCRCACC[28] EXTCRCACC[27] EXTCRCACC[26] EXTCRCACC[25] EXTCRCACC[24] Default 1 1 1 1 1 1 1 1
EXTCRCACC[31:0]: The four registers of EXTCRCACC[31:0] allows the microprocessor to read or write the content of the Extract CRC Accumulator register. The Extract CRC32 Accumulator register accumulates the CRC-32 value of the data being from an Extract FIFO. The rising edge of WRB for two successive write accesses to these registers must separated by at least three REFCLK periods.
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DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x2D: Microprocessor Cell Data Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCDAT[7:0]: The MCDAT[7:0] is used to write to the Insert FIFO or read from the selected Extract FIFO by the microprocessor. When inserting cells, the Insert FIFO Ready register may be polled to determine whether the FIFO is ready to receive a cell. Alternately, an interrupt may be generated by setting the Insert FIFO Interrupt Enable register bit accordingly. A cell is transferred to the Insert FIFO by performing successive write accesses to the Microprocessor Cell Data register. The rising edge of WRB for two successive write accesses to this register must separated by at least three REFCLK periods. When extracting cells, the Extract FIFO Ready register may be polled to determine which FIFO has a cell available to be read. Alternately, an interrupt may be generated by setting the Extract FIFO Interrupt Enable register bit accordingly. Selection of the Extract FIFO is done by writing the EXTFSEL bit of the Extract FIFO Control register. A cell is transferred from an Extract FIFO by performing successive read accesses to the Microprocessor Cell Data register. The falling edge of RDB for two successive read accesses to this register must separated by at least three REFCLK periods. Type R/W R/W R/W R/W R/W R/W R/W R/W Function MCDAT[7] MCDAT[6] MCDAT[5] MCDAT[4] MCDAT[3] MCDAT[2] MCDAT[1] MCDAT[0] Default X X X X X X X X
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Register 0x30: RXD1 Extract FIFO Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UPF1RST: The UPF1RST bit is used to reset the Microprocessor Cell Extract FIFO associated with RXD1+/-. When UPF1RST is set to logic 0, the FIFO operates normally. When UPF1RST is set to logic 1, all the FIFO is immediately emptied and ignores writes. The FIFO remains empty and continues to ignore writes until logic 0 is written to UPF1RST. UPF1OVRE: The UPF1OVRE bit enables the assertion of the INTB output due to an overflow error condition of the Microprocessor Cell Extract FIFO associated with RXD1+/-. When UPF1OVRE is set to logic 1, the interrupt is enabled. R/W R/W Type Function Unused Unused Unused Unused Unused Unused UPF1OVRE UPF1RST Default X X X X X X 0 0
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Register 0x31: RXD1 Extract FIFO Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UPF1OVRI: The UPF1OVRI bit indicates an interrupt due to overflow error condition of the Microprocessor Cell Extract FIFO associated with RXD1+/-. Generally, the UPF1OVRI status bit should never be asserted; its assertion would indicate that the flow control protocol is being ignored. The UPF1OVRI bit is reset immediately after a read to this register. R Type Function Unused Unused Unused Unused Unused Unused Unused UPF1OVRI Default X X X X X X X 0
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Register 0x34: RXD2 Extract FIFO Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UPF2RST: The UPF2RST bit is used to reset the Microprocessor Cell Extract FIFO associated with RXD2+/-. When UPF2RST is set to logic 0, the FIFO operates normally. When UPF2RST is set to logic 1, all the FIFO is immediately emptied and ignores writes. The FIFO remains empty and continues to ignore writes until logic 0 is written to UPF2RST. UPF2OVRE: The UPF2OVRE bit enables the assertion of the INTB output due to an overflow error condition of the Microprocessor Cell Extract FIFO associated with RXD2+/-. When UPF2OVRE is set to logic 1, the interrupt is enabled. R/W R/W Type Function Unused Unused Unused Unused Unused Unused UPF2OVRE UPF2RST Default X X X X X X 0 0
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Register 0x35: RXD2 Extract FIFO Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UPF2OVRI: The UPF2OVRI bit indicates an interrupt due to overflow error condition of the Microprocessor Extract FIFO associated with RXD1+/-. Generally, the UPF2OVRI status bit should never be asserted; its assertion would indicate that the flow control protocol is being ignored. The UPF2OVRI bit is reset immediately after a read to this register. R Type Function Unused Unused Unused Unused Unused Unused Unused UPF2OVRI Default X X X X X X X 0
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Register 0x3C: Receive Logical Channel FIFO Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFORST: The FIFORST bit is used to reset all logical channel FIFOs for the receive link. When FIFORST is set to logic 0, the FIFO channels operate normally. When FIFORST is set to logic 1, all the FIFOs are immediately emptied and ignore writes from the active LVDS link. While the FIFO is reset the flow control information sent to the far end (via the LVDS link) indicates "buffer full or unavailable" for all channels. The FIFOs remain empty and continue to ignore writes until logic 0 is written to FIFORST. To prevent unstable behavior during cell format configuration, FIFORST should be left asserted while changing the cell format or length. If a cell is being transferred from the SCIPHY/Any-PHY output port or from the Clocked Serial Data interface when a reset of the FIFO occurs the cell will be corrupted. When using the SCI-PHY/Any-PHY output port as a bus slave, the bus master need not have started the cell transfer (in response to the asserted OCA from the S/UNI-DUPLEX) for cell corruption to occur. The S/UNIDUPLEX uses a partial look ahead buffer that cannot be reset by the Receive Logical Channel FIFO reset. Even if the bus master suspends cell transfers during the time when the Receive Logical Channel FIFO is reset, the next cell read from the S/UNI-DUPLEX will be corrupted if there was a cell wainting for transfer when the FIFO reset occurred. The simplest approach is to allow the bus master to continue normal operation during a FIFO reset. If required, the bus master can discard any cells received from that link after it is reset. R/W R/W Type Function Unused Unused Unused Unused Unused Unused FOVRE FIFORST Default X X X X X X 0 0
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FOVRE: The FOVRE bit enables the assertion of the INTB output due to a FIFO overrun error condition. When FOVRE is set to logic 1, the interrupt is enabled.
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Register 0x3D:Receive Logical Channel FIFO Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FOVRI: The FOVRI bit indicates an interrupt due to a logical channel FIFO over flow error condition. Generally, the FOVRI status bit should never be asserted; its assertion would indicate that the flow control protocol is being ignored. The FOVRI bit is reset immediately after a read to this register. R Type Function Unused Unused Unused Unused Unused Unused Unused FOVRI Default X X X X X X X X
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Registers 0x40, 0x50: RXD1, RXD2 High-Speed Serial Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Type R/W R/W Function DDSCR HDSCR Unused CNTCELLERR CELLCRC PREPEND USRHDR[1] USRHDR[0] Default 0 1 X 0 0 0 1 0
These registers configure, on a per-link basis, the format of the cells expected on RXD1 and RXD2 serial links.
USRHDR[1:0]: The USRHDR[1:0] bits determine the length of the expected User Header field of the received cells, as illustrated in Fig. 9. USRHDR[1:0] 00 01 10 11 PREPEND: The PREPEND bit determines if the User Prepend field is expected to exist in the received cells. If PREPEND is logic 1, a two byte User Prepend is expected to follow the System Prepend field. CELLCRC: The CELLCRC bit determines whether the entire high-speed serial data structure is expected to be protected by a CRC-8 code word. The PREPEND Bytes in User Header 4 5 6 Reserved
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bit must be logic 1 for this bit to have effect. If CELLCRC and PREPEND are logic 1, the second User Prepend byte is expected to contain the CRC-8 syndrome for the preceding cell. A non-zero remainder shall result in a maskable interrupt and, if enabled by the CNTCELLERR bit, a cell error count increment. If CELLCRC is logic 0, the contents of the second User Prepend byte are not examined. CNTCELLERR: The CNTCELLERR bit allows the redefinition of the Receive High-Speed Serial HCS Error Count register to include the number of cell CRC-8 errors. If CNTCELLERR, CELLCRC and PREPEND are logic 1, each non-zero remainder for the CRC-8 protecting the entire cell or non-zero remainder HCS results in an increment. (Simultaneous cell CRC-8 and HCS errors result in a single increment.) If CNTCELLERR, CELLCRC, and PREPEND are logic 0, the count represents the number of HCS errors. DDSCR and HDSCR: The Disable Descramble (DDSCR) and Header Descramble enable (HDSCR) bits control the descrambling of the cell by the x43 + 1 self-synchronous descrambler. When DDSCR is a logic one, cell header and payload descrambling is disabled. When DDSCR is a logic zero, payload descrambling is enabled and cell header descrambling is determined by HDSCR. HDSCR enables descrambling of the System Prepend, User Prepend, User Header, and HCS byte collectively. The operation of the DDSCR and HDSCR bits is summarized below: DDSCR 1 HDSCR X Operation Cell payload and header descrambling is disabled. THIS CONFIGURATION SHOULD ONLY BE USED FOR DIAGNOSTIC PURPOSES. Cell payload is descrambled. Cell header is left unscrambled. THIS CONFIGURATION SHOULD ONLY BE USED FOR DIAGNOSTIC PURPOSES. Cell payload and header are both descrambled.
0
0
0
1
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Registers 0x41, 0x51: RXD1, RXD2 High-Speed Serial Cell Filtering Configuration/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R/W R/W R Type Function Unused HCSPASS Reserved OCDV Unused ACTV LCDV LOSV Default X 0 0 X X X X X
These registers provide the status of each individual RXD1+/- and RXD2+/serial link. LOSV: The LOSV gives the Loss of Signal state. LOSV becomes logic 1 upon 2048 bit periods (13.2 s at 155.52 Mb/s) without a signal transition in the received data (i.e. before descrambling, if enabled). LOSV becomes logic 0 when a signal transition has occurred in each of 16 consecutive non-overlapping intervals of 16 bit periods each. LCDV: The LCDV bit gives the Loss of Cell Delineation state. When LCDV is logic 1, an out of cell delineation (OCD) defect has persisted for 1318 cells. LCDV becomes logic 0 when cell delineation has been maintained for 1318 cells. LCDV is logic 1 out of reset. ACTV: The ACTV bit provides the debounced state of the ACTIVE bit in the cell prepend. ACTV reflects the state of the ACTIVE bit when it has been the same for three consecutive valid cells. OCDV: The OCDV bit indicates the cell delineation state. When OCDV is logic 1, the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states and is hunting for the cell boundaries. When OCDV is logic 0, the cell delineation
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state machine is in the 'SYNC' state and cells are passed through the receive FIFO. Reserved: This bit must be logic 0 for correct operation. HCSPASS: The HCSPASS bit controls the dropping of cells based on the detection of a HCS error. When HCSPASS is logic 0, cells containing a HCS error are dropped. When HCSPASS is logic 1, non-stuff cells are passed to the FIFO interface regardless of errors detected in the HCS. Stuff cells continue to be dropped and HCS errors continue to be counted by the performance monitor registers. Additionally, the HCS verification finite state machine never exits the `SYNC' state, and hence will never lose cell delineation. This bit is provided for diagnostic purposes only. Regardless of the programming of this bit, cells are always dropped while the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states.
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Registers 0x42, 0x52: RXD1, RXD2 High-Speed Serial Interrupt Enables Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused HCSE XFERE OCDE CELLERRE ACTE LCDE LOSE Default X 0 0 0 0 0 0 0
These registers allow changes in the corresponding RXD1 High-Speed Serial Cell Filtering Configuration/Status and RXD2 High-Speed Serial Cell Filtering Configuration/Status register bits, HCS errors and counter transfers to cause assertion low the INTB output. The Master Interrupt Enable bit of the Master Configuration register must also be logic 1 for the interrupt enables to take effect. LOSE: The LOSE bit enables the generation of an interrupt upon a change in the Loss of Signal state. When LOSE is set to logic 1, the INTB output is asserted low when the LOSI bit is logic 1. LCDE: The LCDE bit enables the generation of an interrupt due to a change in the LCD (Loss of Cell Delineation) state. When LCDE is set to logic 1, the INTB output is asserted low when the LCDI bit is logic 1. ACTE: The ACTE bit enables the generation of an interrupt due to a change in the ACTV register bit. When ACTE is set to logic 1, the INTB output is asserted low when the ACTI bit is logic 1. CELLERRE: The CELLERRE bit enables the generation of an interrupt due to a non-zero remainder of the CRC-8 protecting the entire cell while in the SYNC cell
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delineation state. When CELLERRE , CELLCRC, and PREPEND are set to logic 1, the interrupt is enabled. OCDE: The OCDE bit enables the generation of an interrupt due to a change in cell delineation state. When OCDE is set to logic 1, the INTB output is asserted low when the OCDI bit is logic 1. HCSE: The HCSE bit enables the generation of an interrupt due to the detection of a HCS error while in the SYNC cell delineation state. When HCSE is set to logic 1, the INTB output is asserted low when the HCSI bit is logic 1. XFERE: The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the receive cell counter and HCS error counter holding registers. When XFERE is set to logic 1, the INTB output is asserted low when the XFERI bit is logic 1.
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Registers 0x43,0x53: RXD1, RXD2 High-Speed Serial Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function OVR XFERI HCSI OCDI CELLERRI ACTI LCDI LOSI Default X X X X X X X X
These registers provide an indication of events that have occurred since the last time they were read. These bits are not affected by the programming of the RXD1 and RXD2 High-Speed Serial Interrupt Enables registers, which only determines whether the status of the bits in these registers is propagated to the INTB output. LOSI: The LOSI bit is set to logic 1 whenever the associated LOSV register bit changes state. This bit is reset immediately after a read to this register. LCDI: The LCDI bit is set to logic 1 whenever the associated LCDV register bit changes state. This bit is reset immediately after a read to this register. ACTI: The ACTI bit is set to logic 1 whenever the associated ACTV register bit changes state. This bit is reset immediately after a read to this register. CELLERRI: The CELLERRI bit is set high when a non-zero remainder occurs for the CRC-8 protecting the entire cell. This bit is reset immediately after a read to this register.
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HCSI: The HCSI bit is set high when a HCS error is detected. This bit is reset immediately after a read to this register. XFERI: The XFERI bit indicates that a transfer of accumulated counter data has occurred. A logic 1 in this bit position indicates that the receive cell counter and error counter holding registers have been updated. This update is initiated by writing to the associated (i.e. this link only) Receive High-Speed Serial HCS Error Count register, one of the associated Receive High-Speed Serial Cell Counter registers or the Load Performance Meters (0x000) register. This bit is reset immediately after a read to this register. OCDI: The OCDI bit is set high when the cell delineation state machine enters or exits the SYNC state. The current value of the OCD state is available in the OCDV bit in the associated Receive High-Speed Serial Cell Filtering Configuration/Status register. The OCDI bit is reset immediately after a read to this register. OVR: The OVR bit is the overrun status of the associated accumulation holding registers. A logic 1 in this bit position indicates that a previous transfer (indicated by XFERI being logic 1) has not been acknowledged before the next accumulation interval has occurred, and that the contents of the receive cell counter and HCS error counter holding registers have been overwritten. OVR is set to logic 0 when this register is read.
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Registers 0x44, 0x54: RXD1, RXD2 High-Speed Serial HCS Error Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HCSERR[7:0]: If any of the CELLCRC, CNTCELLERR, and PREPEND bits of the Receive High-Speed Serial Configuration register is logic 0, the HCSERR[7:0] bits indicate the number of HCS error events while in the SYNC cell delineation state that occurred during the last accumulation interval on the associated RXD1+/- or RXD2+/-link. If the CELLCRC, CNTCELLERR, and PREPEND bits are logic 1, the HCSERR[7:0] bits indicate the number of cells with non-zero cell CRC-8 or HCS remainders while in the SYNC cell delineation state. (Simultaneous nonzero cell CRC-8 and HCS remainders result in a single increment).s. The contents of this register become valid a maximum of 300 ns after a transfer is triggered by a write to this register, one of the associated (i.e. this link only) Receive High-Speed Serial Cell Counter registers or the Load Performance Meters (0x00) register, and remain valid until another transfer is triggered. The count saturates at all ones. Type R R R R R R R R Function HCSERR[7] HCSERR[6] HCSERR[5] HCSERR[4] HCSERR[3] HCSERR[2] HCSERR[1] HCSERR[0] Default X X X X X X X X
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Registers 0x45, 0x55: RXD1, RXD2 High-Speed Serial Cell Counter (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RCELL[7] RCELL[6] RCELL[5] RCELL[4] RCELL[3] RCELL[2] RCELL[1] RCELL[0] Default X X X X X X X X
Registers 0x46, 0x56: RXD1, RXD2 High-Speed Serial Cell Counter Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RCELL[15] RCELL[14] RCELL[13] RCELL[12] RCELL[11] RCELL[10] RCELL[9] RCELL[8] Default X X X X X X X X
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Registers 0x47, 0x57: RXD1, RXD2 High-Speed Serial Cell Counter (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCELL[23:0]: The RCELL[23:0] bits indicate the number of valid cells received during the last accumulation interval. Cells filtered due to HCS errors or as stuff cells are not counted. No cells are transferred when the cell delineation state machine is in either the HUNT or PRESYNC state. Cells lost due to FIFO overflows are excluded from the count. The counter should be polled at least every 30 seconds to avoid saturation. The contents of these registers become valid a maximum of 300 ns after a transfer is triggered by a write to these registers, the associated Receive High-Speed Serial HCS Error Count register or the Load Performance Meters (0x00) register, and remain valid until another transfer is triggered. The count saturates at all ones. Type R R R R R R R R Function RCELL[23] RCELL[22] RCELL[21] RCELL[20] RCELL[19] RCELL[18] RCELL[17] RCELL[16] Default X X X X X X X X
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Register 0x5C: Transmit Logical Channel FIFO Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFORST: The FIFORST bit is used to reset all the logical channels of the Transmit Logical Channel FIFO. When FIFORST is set to logic 0, the FIFO channels operate normally. When FIFORST is set to logic 1, all the FIFOs are immediately emptied and ignore writes. The FIFOs remain empty and continue to ignore writes until logic 0 is written to FIFORST. This results in a continuous stream of stuff cells on TXD1+/- and TXD2+/-. If a user cell is currently being sent over the LVDS link it will likely be corrupted by the reset. If the header portion of the cell has been sent then this corruption will not be detected at the receiver if header error detection is enabled. However it will likely be detected if cell error detection is enabled. See Transmit High-Speed Serial Configuration Register, CELLCRC bit, and RXD1, RXD2 Serial Configuration Register, CELLCRC bit for details. FOVRE: The FOVRE bit enables the generation of an interrupt due to a FIFO overrun error condition. When FOVRE and the Master Interrupt Enable bit of the Master Configuration register are set to logic 1, the interrupt is enabled. R/W R/W Type Function Unused Unused Unused Unused Unused Unused FOVRE FIFORST Default X X X X X X 0 0
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Register 0x5D: Transmit Logical Channel FIFO Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FOVRI: The FOVRI bit indicates an interrupt due to a Transmit Logical Channel FIFO overrun error condition. This interrupt is generated when a write attempt is performed to a FULL channel. Generally, the FOVRI status bit should never be asserted; its assertion would indicate that the flow control protocol is being ignored. This bit is reset immediately after a read to this register. R Type Function Unused Unused Unused Unused Unused Unused Unused FOVRI Default X X X X X X X X
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Register 0x5E: Transmit Logical Channel FIFO Depth Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W Type Function Unused Unused FDEPTH[5] FDEPTH[4] FDEPTH[3] FDEPTH[2] FDEPTH[1] FDEPTH[0] Default X X 0 0 0 0 1 0
FDEPTH[5:0]: The FDEPTH[5:0] bits are used to set the total number of available cells per logical channel of the Transmit FIFO. The value of FDEPTH[5:0] varies according to the configuration of the modem interface. If the SCI-PHY interface is used (the SCYPHY pin is set to logic 1), the FIFO Depth is to be set to 0b000010. If the Clock Serial Data Interface is used, the FIFO depth is to be set to 0b000100. Setting FDEPTH[5:0] to others values may cause FIFO malfunction.
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Register 0x60: Transmit High-Speed Serial Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Type R/W R/W Function DSCR HSCR Unused DHCS CELLCRC PREPEND USRHDR[1] USRHDR[0] Default 0 1 X 0 0 0 1 0
This register configures the format of the cells transmitted on both the TXD1+/and the TXD2+/- serial links. USRHDR[1:0]: The USRHDR[1:0] bits determine the length of the User Header field of the transmitted cells. The User Header defaults to six bytes. USRHDR[1:0] 00 01 10 11 PREPEND: The PREPEND bit determines if the User Prepend field is inserted into the transmitted cells. If PREPEND is logic 1, a two byte User Prepend is inserted after the System Prepend field. CELLCRC: The CELLCRC bit determines whether the entire high-speed serial data structure is protected by a CRC-8 code word. The PREPEND bit must be logic 1 for this bit to have effect. If CELLCRC and PREPEND are logic 1, the second User Prepend byte is overwritten by the CRC-8 syndrome for the Bytes in User Header 4 5 6 Reserved
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preceding cell. If CELLCRC is logic 0, the contents of the second User Prepend byte are transported transparently. DHCS: The DHCS bit controls the insertion of HCS errors for diagnostic purposes. When DHCS is set to logic one, the HCS octet for a single cell is inverted prior to insertion. After the insertion, DHCS is automatically reset to logic 0. To invert the HCS octet in another cell, DHCS must be set to logic 1 again. DSCR and HSCR: The Disable Scramble enable (DSCR) and Header Scramble enable (HSCR) bits control the scrambling of the cell. When DSCR is logic one, cell header and payload scrambling is disabled. When DSCR is logic zero, payload scrambling is enabled and cell header scrambling is determined by HSCR. HSCR enables scrambling of the System Prepend, User Prepend, User Header, and HCS byte collectively. The operation of the DSCR and HSCR bits is summarized below: DSCR 1 0 HSCR X 0 Operation Cell payload and header scrambling is disabled. THIS CONFIGURATION SHOULD ONLY BE USED FOR DIAGNOSTIC PURPOSES. Cell payload is scrambled. Cell header is left unscrambled. THIS CONFIGURATION SHOULD ONLY BE USED FOR DIAGNOSTIC PURPOSES. Cell payload and header are both scrambled.
0
1
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Register 0x61: Transmit High-Speed Serial Cell Count Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R R Function XFERE XFERI OVR Unused Unused Unused Unused Unused Default 0 X X X X X X X
This register indicates whether the associated Transmit Cell Count registers have been updated with new data and whether this data overwrites unacknowledged data. OVR: The OVR bit is the overrun status of the associated Transmit Cell Count registers. A logic 1 in this bit position indicates that a previous transfer (indicated by XFERI being logic 1) has not been acknowledged before the next accumulation interval has occurred and thus the contents of the Transmit Cell Count registers have been overwritten. OVR is set to logic 0 when this register is read. XFERI: The XFERI bit indicates that a transfer of Transmit Cell Count data has occurred. A logic 1 in this bit position indicates that the associated Transmit Cell Count registers have been updated. This update is initiated by writing to one of the associated Transmit Cell Count register locations or by writing to the Load Performance Meters (0x000) register. XFERI is set to logic 0 when this register is read. XFERE: The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the associated Transmit Cell Count registers. When XFERE and the Master Interrupt Enable bit of the Master Configuration register are set to logic 1, the INTB output is asserted low if the XFERI bit is a logic 1.
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Register 0x62: Transmit High-Speed Serial Cell Counter (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TCELL[7] TCELL[6] TCELL[5] TCELL[4] TCELL[3] TCELL[2] TCELL[1] TCELL[0] Default X X X X X X X X
Register 0x63: Transmit High-Speed Serial Cell Counter Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TCELL[15] TCELL[14] TCELL[13] TCELL[12] TCELL[11] TCELL[10] TCELL[9] TCELL[8] Default X X X X X X X X
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Register 0x64: Transmit High-Speed Serial Cell Counter (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCELL[23:0]: The TCELL[23:0] bits indicate the number of cells inserted into the transmission stream during the last accumulation interval. Stuff cells inserted into the transmission stream for rate decoupling are not counted. A write to any one of the Transmit Cell Counter registers for a particular serial link or a write to the Load Performance Meters (0x00) register loads the registers with the current counter value and resets the internal 24 bit counter. The counter should be polled at least every 30 seconds to avoid saturating. The contents of these registers become valid within 300 ns after a transfer is triggered by a write to any of the link-associated Transmit Cell Count registers or to the Load Performance Meters (0x00) register, and remain valid until another transfer is triggered. The count saturates at all ones. Type R R R R R R R R Function TCELL[23] TCELL[22] TCELL[21] TCELL[20] TCELL[19] TCELL[18] TCELL[17] TCELL[16] Default X X X X X X X X
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Register 0x68: Receive Serial Indirect Channel Select Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type R R/W R/W Function CBUSY CRWB DRHCSE Unused CHAN[3] CHAN[2] CHAN[1] CHAN[0] Default X 0 0 X 0 0 0 0
This register provides the channel number used to access the channel provision RAM of the receive Clocked Serial Data Interface. Writing to this register triggers an indirect channel register access. CHAN[3:0]: The indirect channel number bits (CHAN[3:0]) indicate the channel to be configured or interrogated in the indirect access. DRHCSE: Disable Reset of the HCS Error Count (DRHCSE) disables automatic reset of the HCS Error Counter (HCSERR). When the bit is set to logic 0, automatic reset of the HCS Error Counter is enabled. If an indirect read is initiated (i.e., CRWB written with logic 1) with DRHCSE logic 0, the HCS Error Counter is reset to zero upon completion of the indirect read. When the DRHCSE bit is set to logic 1, automatic reset of the HCS Error Counter is disabled. CRWB: The channel indirect access control bit (CRWB) selects between a configure (write) or interrogate (read) access to the channel provision RAM. Writing a logic 0 to CRWB triggers an indirect write operation. Data to be written is taken from the Receive Serial Indirect Channel Data registers. Writing a logic 1 to CRWB triggers an indirect read operation. The data read can be found in the Receive Serial Indirect Channel Data registers.
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CBUSY: The indirect access status bit (CBUSY) reports the progress of an indirect access. CBUSY is set to logic 1 when a write to the Receive Serial Indirect Channel Select register triggers an indirect access and will remain logic 1 until the access is complete. This register should be polled to determine when data from an indirect read operation is available in the Receive Serial Indirect Channel Data registers or to determine when a new indirect write operation may commence. The CBUSY is not expected to remain at logic 1 for more than two REFCLK cycles.
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Register 0x69: Receive Serial Indirect Channel Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W Function PROV HCSPASS UNASSFLTR IDLEPASS DDSCR Reserved DDELIN Unused Default 0 0 0 0 0 0 0 X
This register contains data read from the channel provision RAM of the Receive Clocked Serial Data Interface after an indirect channel read operation or data to be inserted into the channel provision RAM in an indirect channel write operation. The bits to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. The bits reflect the value written until the completion of a subsequent indirect channel read operation. The reset state of the bits enables standard ATM cell processing as stipulated in ITU-T Recommendation I.432.1. DDELIN: The indirect disable delineate enable bit (DDELIN) configures the TC processor to perform cell delineation and header error detection on the incoming data stream. When DDELIN is set to logic 0, the cell alignment is established and maintained on the incoming data stream. When DDELIN is set to logic 1, the RTTC does not perform any processing on the incoming stream, but passes data through transparently. Reserved: This bit must be logic 0 for correct operation.
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DDSCR: The DDSCR bit controls the descrambling of the cell payload with the polynomial x43 + 1. When DDSCR is set to logic 1, cell payload descrambling is disabled. When DDSCR is set to logic 0, payload descrambling is enabled. IDLEPASS: The IDLEPASS bit controls the function of the idle cell filter. When IDLEPASS is written with a logic 0, all idle cells (first four bytes of cell are `H00, `H00, `H00, `H01) are filtered out. When IDLEPASS is logic 1, idle cells are passed on to the cell buffer. UNASSPASS: When UNASSPASS is written with a logic 0, all unassigned cells (first four bytes of cell are `H00, `H00, `H00, `H00) are filtered out. When UNASSPASS is logic 1, unassigned cells are passed on the cell buffer. HCSPASS: The HCSPASS bit controls the dropping of cells based on the detection of an HCS error. When HCSPASS is logic 0, cells containing an HCS error are dropped. When HCSPASS is a logic 1, cells are passed to the external cell buffer regardless of errors detected in the HCS. Regardless of the programming of this bit, cells are always dropped while the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the channel provision RAM after an indirect channel read operation has completed. When PROV is set to logic 1, the TC processor will process data on the channel specified by CHAN[3:0]. When PROV is set to logic 0, the TC processor will ignore data on the channel specified by CHAN[3:0].
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Register 0x6A: Receive Serial Indirect Channel Interrupt Enables Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type Function Unused Unused Unused Unused OOCDE HCSE FOVRE LCDE Default X X X X 0 0 0 0
This register contains data read from the channel provision RAM of the Receive Clocked Serial Data Interface after an indirect read operation or data to be inserted into the channel provision RAM in an indirect write operation. The bits to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. The bits reflect the value written until the completion of a subsequent indirect channel read operation. LCDE: The LCDE bit enables the generation of an interrupt due to a change in the LCD state. When LCDE is set to logic 1, the interrupt is enabled. FOVRE: The FOVRE bit enables the generation of an interrupt due to a FIFO overrun error condition. When FOVRE is set to logic 1, the interrupt is enabled. HCSE: The HCSE bit enables the generation of an interrupt due to the detection of an HCS error. When HCSE is set to logic 1, the interrupt is enabled. OOCDE: The OOCDE bit enables the generation of an interrupt due to a change in cell delineation state. When OOCDE is set to logic 1, the interrupt is enabled.
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Register 0x6B: Receive Serial Indirect Channel Interrupt and Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type R R Function OOCDV LCDV Unused Unused OOCDI HCSI FOVRI LCDI Default X X X X X X X X
This register contains data read from the channel provision RAM of the Receive Clocked Serial Data Interface after an indirect read operation. LCDI: The LCDI bit is set to logic 1 when there is a change in the loss of cell delineation (LCD) state. This bit is reset immediately after a read to this register. FOVRI: The FOVRI bit is set to logic 1 when a FIFO overrun has occurred or is about to occur. Normally the occurrence of the FOVRI interrupt indicates that one or more user cells have been discarded due to the buffer overflow condition. However, if the overflow pending condition exists only temporarily (and when only IDLE cells are being received) it is possible that no user cells were actually discarded. This bit is reset immediately after a read to this register. HCSI: The HCSI bit is set to logic 1 when an HCS error is detected. This bit is reset immediately after a read to this register. OOCDI: The OOCDI bit is set to logic 1 when the logical channel enters or exits the SYNC state. The OOCDV bit indicates whether the logical channel is in the SYNC state or not. The OOCDI bit is reset immediately after a read to this register.
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LCDV: The LCDV bit gives the Loss of Cell Delineation state. When LCD is logic 1, an out of cell delineation (OCD) defect has persisted for the number of cells specified in the LCD Count Threshold register. When LCD is logic 0, no OCD has persisted for the number of cells specified in the LCD Count Threshold register. The cell time period can be varied by using the LCDC[7:0] register bits in the LCD Count Threshold register. OOCDV: The OOCDV bit is set to logic 1 when the logical channel is not currently in the SYNC state.
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Register 0x6C: Receive Serial Indirect Channel HCS Error Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function HCSERR[7] HCSERR[6] HCSERR[5] HCSERR[4] HCSERR[3] HCSERR[2] HCSERR[1] HCSERR[0] Default X X X X X X X X
This register contains data read from the channel provision RAM of the Receive Clocked Serial Data Interface after an indirect read operation. HCSERR[7:0]: The HCSERR[7:0] bits indicate the number of HCS error events that occurred during the last accumulation interval of the receive Clock Serial Data Interface. When the number of HCS error events during the last accumulation interval exceeds 255, the HCSERR[7:0] retains value of FFH until the next accumulation interval.
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Register 0x6D: Receive Serial LCD Count Threshold Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCDC[7:0]: The LCDC[7:0] bits represent the number of consecutive cell periods the receive cell processor of the Clock Serial Data Interface must be out of cell delineation before loss of cell delineation (LCD) is declared. Likewise, LCD is not deasserted until the receive cell processor is in cell delineation for the number of cell periods specified by LCDC[7:0]. The default value of LCD[7:0] of 104 translates to 73 ms at 600 kb/s. Type R/W R/W R/W R/W R/W R/W R/W R/W Function LCDC[7] LCDC[6] LCDC[5] LCDC[4] LCDC[3] LCDC[2] LCDC[1] LCDC[0] Default 0 1 1 0 1 0 0 0
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Register 0x70: Transmit Serial Indirect Channel Select Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type R R/W Function CBUSY CRWB Unused Unused CHAN[3] CHAN[2] CHAN[1] CHAN[0] Default X 0 X X 0 0 0 0
This register provides the channel number used to access the channel provision RAM of the transmit Clocked Serial Data Interface. Writing to this register triggers an indirect channel register access. CHAN[3:0]: The indirect channel number bits (CHAN[3:0]) indicate the channel to be configured or interrogated in the indirect access. CRWB: The channel indirect access control bit (CRWB) selects between a configure (write) or interrogate (read) access to the channel provision RAM. Writing a logic zero to CRWB triggers an indirect write operation. Data to be written is taken from the Transmit Serial Indirect Channel Data registers. Writing a logic one to CRWB triggers an indirect read operation. The read can be found in the Transmit Serial Indirect Channel Data registers. CBUSY: The indirect access status bit (CBUSY) reports the progress of an indirect access. CBUSY is set to logic 1 when a write to the Transmit Serial Indirect Channel Select register triggers an indirect access and will stay high until the access is complete. This register should be polled to determine when data from an indirect read operation is available in the Transmit Serial Indirect Channel Data registers or to determine when a new indirect write operation may commence.
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Register 0x71:Transmit Serial Indirect Channel Data Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W Function DHCS HSCR DSCR Unused Unused Unused Unused Unused Default 0 0 0 X X X X X
This register contains data read from the channel provision RAM of the Transmit Clocked Serial Data Interface after an indirect channel read operation or data to be inserted into the channel provision RAM in an indirect channel write operation. DSCR: The indirect scrambling disable bit (DSCR) configures scrambling. The scramble disable bit to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When DSCR is logic 1, scrambling is disabled. When DSCR is logic 0, either the 48 byte payload or the entire bit stream (if HSCR is logic 1) is scrambled. DSCR reflects the value written until the completion of a subsequent indirect channel read operation. HSCR: The indirect header scrambling enable bit (HSCR) configures header scrambling. The header scramble enable bit to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When HSCR is logic 1 and DSCR is logic 0, the header is scrambled in addition to the payload. When HSCR is logic 0 and DSCR is logic 0, only the cell payload is scrambled. HSCR reflects the value written until the completion of a subsequent indirect channel read operation.
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DHCS: The Disable HCS (Header Check Sequence) bit (DHCS) configures the insertion of the HCS in the fifth byte of the cell. The value of DHCS to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When DHCS is logic 0, the CRC-8 calculation over the first four bytes of the cell overwrites the fifth byte. When DHCS is logic 1, the fifth byte of the cell passes through unmodified. (It is still subject to scrambling.) DHCS reflects the value written until the completion of a subsequent indirect channel read operation.
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Register 0x74:Transmit Serial Alignment Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ALIGN: The alignment enable bit (ALIGN) allows ATM/Data octet alignment to frame boundaries based on recognizing gaps in the clock. When this bit is set to logic 1, the ATM /Data octets are aligned to the inferred frame alignment, with the most significant bit output first during the clock gap. No frame alignment is inferred when this bit is set to logic 0. To be detected, the gap polarity must match the value of the LTXCINV bit of the Master Configuration register. When the rising edge of clock signals on LTXC[15:0] is used to output the data (LTXCINV set to logic 0), gaps during which the clock is forced to logic 0 are detected. When the falling edge of the clock signals on LTXC[15:0] are used to output the data (LTXCINV set to logic 1), gaps during which the clock is forced to logic 1 are detected. R/W Type Function Unused Unused Unused Unused Unused Unused Unused ALIGN Default X X X X X X X 0
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11
TEST FEATURES DESCRIPTION Simultaneously asserting (low) the CSB, RDB and WRB inputs causes all digital output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing. Test mode registers are used to apply test vectors during production testing of the S/UNI-DUPLEX. Test mode registers (as opposed to normal mode registers) are selected when TRS (A[7]) is high. The S/UNI-DUPLEX supports a standard IEEE 1149.1 five-signal JTAG boundary scan test port for use in board testing. All digital device inputs may be read and all digital device outputs may be forced with the exception of the RXD1+/-, RXD2+/-, TXD1+/- and TXD2+/- pins via the JTAG test port. A limited RAM built-in-self-test (BIST) is available. Notes on Test Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. Writable test mode register bits are not initialized upon reset unless otherwise noted.
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Register 0x80: Master Test Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W W W W R/W W R/W Type Function Unused Reserved PMCATST PMCTST DBCTRL IOTST HIZDATA HIZIO Default X 0 X X X 0 X 0
This register is used to enable S/UNI-DUPLEX test features. All bits, except PMCTST and PMCATST, are reset to zero by a reset or a software reset of the S/UNI-DUPLEX. HIZIO, HIZDATA: The HIZIO and HIZDATA bits control the tri-state modes of the S/UNIDUPLEX. While the HIZIO bit is a logic one, all output pins of the S/UNIDUPLEX except the data bus and output TDO are held tri-state. The microprocessor interface is still active. While the HIZDATA bit is a logic one, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. The HIZDATA bit is overridden by the DBCTRL bit. IOTST: The IOTST bit is used to allow normal microprocessor access to the test registers and control the test mode in each TSB block in the S/UNI-DUPLEX for board level testing. When IOTST is a logic one, all blocks are held in test mode. DBCTRL: The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin. When the DBCTRL bit is set to logic one and either IOTST or PMCTST are logic one, the CSB pin controls the output enable for the data bus. While the DBCTRL bit is set, holding the CSB pin high causes the S/UNI-DUPLEX to drive the data bus and holding the CSB pin low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads.
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PMCTST: The PMCTST bit is used to configure the S/UNI-DUPLEX for PMC's manufacturing tests. When PMCTST is set to logic one, the S/UNI-DUPLEX microprocessor port becomes the test access port used to run the PMC "canned" manufacturing test vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and can be cleared by setting CSB to logic one or by writing logic zero to the bit. PMCATST: The PMCATST bit is used to configure the analog portion of the S/UNIDUPLEX for PMC's manufacturing tests. PMCATST is cleared when CSB is high and RSTB is low or when PMCATST is written as logic 0. Register 0x83: Miscellaneous Test Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLKSEL[2:0]: The CLKSEL[2:0] bits can be used to output a internally generated clock on the RX8K output to increase the observability of the device for test purpose. When CLKSEL[2:0] is set to 0b00 (default mode), the RX8K output is extracted from one of the receive high-speed serial links, RXD1+/- or RXD2+/-. When set to other values, an internally generated clock is muxed on the RX8K output, as described in the following table: CLKSEL[2:0] 00000 00001 00010 Clock RX8K ACT_RCLK SYSCLK R/W R/W R/W R/W R/W R/W Type Function Unused Unused TCADIS LINKSELBP SELOCD CKLSEL[2] CLKSEL[1] CLKSEL[0] Default X X 0 0 0 0 0 0
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00011 00100 00101 00110 00111 SELOCD:
CSDCLK DCLK CCLK L1_RCLK L2_RCLK
The SELOCD bit allows usage of the OCD signal instead of the LCD signal to gate to gate the ACTIVEBIT extracted from the high-speed serial links. This is useful to speed up simulation, LCD being a very slow signal. LINKSELBP: The LINKSELBP allows to bypass the sequenced automatic link selection circuit. When LINKSELBP is set to logic 1, the high-speed serial link selection is immediate. When set to logic 0, the high-speed serial link selection will be performed prior just prior to an incoming cell (idle or data) on the "to be active" serial link. TCADIS: The TCADIS bit disables the transmission of the flow control information in the upstream direction of the inactive high-speed serial link. Its usage is intended for test purposes. When set to logic 1, the S/UMI-DUPLEX will indicates on the inactive high-speed serial link that it can not accept cells on any logical channel. When set to logic 0, the flow control bits for the logical channel are identical to the flow control bits of the active channel. The flow control bits of the active high-speed serial link are not affected by the TCADIS. 11.1 RAM Built-In-Self-Test The S/UNI-DUPLEX contains built-in-self-test (BIST) circuitry for production testing of the device. A subset of the functionality is available for in situ screening against damage during handling and board manufacture. The tests are controlled through the microprocessor port. Clock signals need to be applied to the device. The only other signals involved are the REFCLK, TCK and TX8K inputs. 11.1.1 128x8 RAM The following procedure tests the six 128x8 RAMs simultaneously:
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1. Hold REFCLK, TCK and TX8K low. 2. Set the RESET bit of the Master Reset and Identity register (0x00) to logic 1 to place the device in a known state. 3. Write the following register locations to select the test mode and initialize the BIST circuitry: 1. Write 0x02 to 0xB1, 0xB5, 0xB9 2. Write 0x01 to 0xB0, 0xB4, 0xB8 3. Write 0x55 to 0xB2, 0xB6, 0xBA These registers do not have default values and must be written. 4. Clear the RESET bit of the Master Reset and Identity register (0x00) to logic 0. 5. Set the IOTST bit of the Master Test register (0x80) to logic 1. This activates the BIST test mode. 6. Start toggling the REFCLK, TCK and TX8K inputs at up to a maximum frequency of 4 MHz. All clocks need be phase and frequency locked. 7. After exactly 2045 clock cycles read the following registers and compare against the expected data. Any discrepancies represent a test failure. The two bits being compared are flags that are cleared when at least one RAM bit location returns an incorrect value. Letting the test run indefinitely simply causes the test sequences to be repeated. A[7:0] 0xB2, 0xB6, 0xBA 11.1.2 2048x8 RAM The following procedure tests the two 2048x8 RAMs: simultaneously: 1. Hold REFCLK and TCK low. 2. Set the RESET bit of the Master Reset and Identity register (0x00) to logic 1 to place the device in a known state. 3. Write the following register locations to select the test mode and initialize the BIST circuitry: Expected D[7:0] xxxx0011
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1. Write 0x02 to 0xDD 2. Write 0x01 to 0xDC 3. Write 0x55 to 0xDE These registers do not have default values and must be written. 4. Clear the RESET bit of the Master Reset and Identity register (0x00) to logic 0. 5. Set the IOTST bit of the Master Test register (0x80) to logic 1. This activates the BIST test mode. 6. Start toggling the REFCLK and TCK inputs at up to a maximum frequency of 4 MHz. All clocks need be phase and frequency locked. 7. After exactly 32765 clock cycles read the following register and compare against the expected data. Any discrepancies represent a test failure. The two bits being compared are flags that are cleared when at least one RAM bit location returns an incorrect value. Letting the test run indefinitely simply causes the test sequences to be repeated. A[7:0] 0xDE 11.1.3 4096x8 RAM The following procedure tests the two 4096x8 RAMs simultaneously: 1. If SCIANY is set to logic 1, OFCLK and REFCLK are to be used. If SCIANY is set to logic 0, TCK and REFCLK are used. Keep clock signals low. 2. Set the RESET bit of the Master Reset and Identity register (0x00) to logic 1 to place the device in a known state. 3. Write the following register locations to select the test mode and initialize the BIST circuitry: 1. Write 0x02 to 0xBD 2. Write 0x01 to 0xBC 3. Write 0x55 to 0xBE Expected D[7:0] xxxx0011
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These registers do not have default values and must be written. 4. Clear the RESET bit of the Master Reset and Identity register (0x00) to logic 0. 5. Manually select link 1 as the active link by writing 0x00 to the Master Configuration register (0x01). 6. Set the IOTST bit of the Master Test register (0x80) to logic 1. This activates the BIST test mode. 7. Start toggling the OFCLK and REFCLK or TCK and REFCLK (depending on the SCIANY input) at up to a maximum frequency of4 MHz. Both clocks need be phase and frequency locked. 8. After 65533 clock cycles read the following register and compare against the expected data. Any discrepancies represent a test failure. The two bits being compared are flags that are cleared when at least one RAM bit location returns an incorrect value. Letting the test run indefinitely simply causes the test sequences to be repeated. A[7:0] 0xBE Expected D[7:0] xxxx0011
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11.2
JTAG Test Port The S/UNI-DUPLEX JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section. Instruction Register Length - 3 bits Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Selected Register Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass Instruction Codes, IR[2:0] 000 001 010 011 100 101 110 111
Identification Register Length - 32 bits Version number - 1H Part Number - 7350H Manufacturer's identification code - 0CDH Device identification - 173500CDH (with CDSDIS tied to VSS). Length - 100 bits Table 18: Boundary Scan Register Pin/Enable
hiz_oen rstob ica_lrxc_13
Register Cell Bit Type
0 1 2
Enable Pin/Enable
oavalid_lrxd_1 oenb_lrxd_2 oca_lrxc_2
Register Cell Bit Type
50 51 52 IO_CELL IO_CELL IO_CELL
Enable
octrl_oen octrl_oen oca_oen
ENABLE OUT_CELL IO_CELL ica_oen
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ica_oen ienb_lrxd_13 iaddr_0_lrxc_14 iaddr_1_lrxd_14 ictrl_oen iaddr_2_ltxc_14 iaddr_3_lrxc_15 iaddr_4_lrxd_15 iavalid_ltxc_15 ibus8_ltxd_14 imaster_ltxd_15 intb sciany csb rdb ale wrb a[7] a[6] a[5] rstb a[4] a[3] a[2] a[1] a[0] tx8k d[7] d[6] d[5] d[4] rclk d_oen rx8k d[3] d[2] d[1] d[0] ltxd_0 refclk omaster_ltxd_1 oaddr_0_lrxc_0 oaddr_1_lrxd_0 oaddr_2_ltxc_0 octrl_oen
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
ENABLE IO_CELL IO_CELL IO_CELL ENABLE IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IO_CELL IO_CELL IO_CELL IO_CELL OUT_CELL ENABLE OUT_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IN_CELL IO_CELL IO_CELL IO_CELL IO_CELL ENABLE
oca_oen ictrl_oen osx_lrxc_3 ictrl_oen osoc_lrxd_3 ictrl_oen odat_0_ltxc_2 odat_1_lrxc_4 ictrl_oen odat_2_lrxd_4 ictrl_oen odat_3_lrxd_5 ictrl_oen odat_4_lrxc_6 ictrl_oen oanyphy_ltxd_2 csd_oen ofclk_lrxc_5 csd_oen obus8_ltxd_4 odat_5_lrxd_6 odat_oen odat_6_lrxc_7 odat_7_lrxd_7 odat_8_ltxc_3 ltxd_3 odat_9_ltxc_4 odat_10_lrxc_8 odat_11_lrxd_8 odat_12_ltxc_5 odat_13_lrxc_9 odat_14_lrxd_9 odat_15_lrxc_10 oprty_lrxd_10 ianyphy_ltxd_5 csd_oen d_oen isx_ltxc_6 d_oen isoc_ltxd_6 d_oen idat_0_ltxc_7 d_oen idat_1_ltxd_7 hiz_oen idat_2_ltxc_8 idat_3_ltxd_8 hiz_oen idat_4_ltxd_9 d_oen ifclk_ltxc_9 d_oen idat_5_ltxc_10 d_oen idat_6_ltxd_10 d_oen idat_7_lrxc_11 csd_oen idat_8_lrxd_11 idat_9_ltxc_11 csd_oen idat_10_ltxd_11 octrl_oen idat_11_lrxc_12 octrl_oen idat_12_lrxd_12 octrl_oen idat_13_ltxc_12 idat_14_ltxd_12
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97
OUT_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IN_CELL IO_CELL IO_CELL ENABLE IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL IO_CELL ENABLE IN_CELL IO_CELL IN_CELL IO_CELL IN_CELL IO_CELL IO_CELL IN_CELL IN_CELL IO_CELL IN_CELL IN_CELL IN_CELL IO_CELL IN_CELL IN_CELL IN_CELL IO_CELL
odat_oen odat_oen odat_oen odat_oen odat_oen odat_oen odat_oen csd_oen csd_oen odat_oen odat_oen odat_oen odat_oen csd_oen odat_oen odat_oen odat_oen odat_oen odat_oen odat_oen odat_oen odat_oen csd_oen
csd_oen csd_oen csd_oen csd_oen
csd_oen
csd_oen
csd_oen
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oaddr_3_ltxc_1 oaddr_4_lrxc_1
48 49
IO_CELL IO_CELL
octrl_oen idat_15_ltxc_13 octrl_oen iprty_ltxd_13
98 99
IN_CELL IO_CELL
csd_oen
NOTES: 1. When set high, HIZ_OEN forces all OUT_CELL and IO_CELL except INTB and RSTOB to high impedance. 2. RX8K_OEN is the first bit of the boundary scan chain scanned in and out.
11.2.1
Boundary Scan Cells In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the Boundary Scan Register table located above. Fig. 12 Input Observation Cell (IN_CELL)
IDCODE Scan Chain Out INPUT to internal logic
Input Pad
G1 G2 SHIFT-DR
I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
Scan Chain In
D C
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Fig. 13 Output Cell (OUT_CELL)
Scan Chain Out EXTEST OUTPUT or Enable f rom syst em logic IDCODE SHIFT - DR
G1 1 G1 G2 1 1 1 1 2 2 MUX 2 2 1
OUTPUT or Enable
MUX
D C
D C
I.D. code bit CLOCK-DR UPDA TE- DR
Scan Chain In
Fig. 14 Bidirectional Cell (IO_CELL)
Scan Chain Out
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin I.D. code bit CLOCK-DR UPDATE-DR Scan Chain In
G1 1 G1 G2 12 1 2 MUX 12 12 D C D C 1
INPUT to internal logic
MUX
OUTPUT to pin
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Fig. 15 Layout of Output Enable and Bidirectional Cells
Scan Chain Out OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic
OUT_CELL
IO_CELL
I/O PAD
Scan Chain In
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12
OPERATION
12.1 Microprocessor Inband Communication
In the upstream direction, the S/UNI-DUPLEX broadcasts control channel cells on both the active and spare high-speed serial links. The contents of the cells shall distinguish the two control channels if necessary. In the downstream direction, each high-speed serial link has a dedicated queue for the control channel cells. The S/UNI-DUPLEX includes hardware support for CRC-32 generation and verification. It consists of two accumulator registers, the Insert CRC-32 Accumulator register for control channel in the upstream direction and the Extract CRC-32 Accumulator for control channel in the downstream direction. To allow context change, each accumulator register can be preset, read and written by the microprocessor.
12.1.1 Inserting Cells Into Control Channels
Cells are inserted into control channels by manipulating the Microprocessor Insert FIFO Control and Microprocessor Insert FIFO Ready registers. The following steps are required to insert a cell: 1. Poll the INSRDY bit in the Microprocessor Insert FIFO Ready. Alternately, service the interrupts that result from setting the INSRDYE bit in the Microprocessor Cell Buffer Interrupt Control and Status register. 2. If CRC-32 calculation is required set the INSCRCPR of the Microprocessor Insert FIFO Control register to logic 0 to enable the CRC-32 process. The Insert CRC-32 Accumulation register can be preset by writing a logic 1 to INSCRCPR prior to enabling the CRC-32 calculation. If the cell is not the first of the message, write the Insert CRC-32 Accumulator register with the value stored at the end of the previous cell for the same control channel. This step is not necessary if the last cell inserted belonged to the same control channel as the current cell. Insertion of the CRC-32 field is done by setting the INSCRCEND bit of the Microprocessor Insert FIFO Control register to logic 1 prior to writing the last cell of the CPCS-PDU. The S/UNI-DUPLEX will overwrite the data of the last four bytes of the cell payload written by the microprocessor with the ones complement of the content of the Insert CRC-32 Accumulator register.
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3. Write the cell content to the Microprocessor Cell Data register. Cell data is entered in the format illustrated in Fig. 11. 4. If the cell is not the last of the message, read and store the contents of the Insert CRC-32 accumulator register. This step is not necessary if the next cell to be inserted belongs to the same control channel as the current cell. The above sequence is repeated as needed to insert more cells. The assertion of the INSRDY bit of the Insert FIFO indicates that the FIFO is ready again to be written to. Setting INSRST of the Insert FIFO Control register to logic 1 prior to writing the last cell byte allows the overwriting of the cell data.
12.1.2 Reading Cell Data From a Control Channel
Reading cell data from a control channel is done by manipulating the Microprocessor Extract FIFO Control and Microprocessor Extract FIFO Ready registers. The following steps are required to read a cell from one of the Extract FIFOs. 1. Poll the bit of EXTRDY[1:0] in the Microprocessor Extract FIFO Ready registerhigh-speed. The EXTRDY[0] and EXTRDY[1] bits indicate the status of the FIFO receiving control channel cells from the RXD1+/- and RXD2+/high-speed links, respectively. Alternately, service the interrupts that result from setting the EXTRDYE bit in the Microprocessor Cell Buffer Interrupt Control and Status register. 2. Select the Extract FIFO corresponding to the desired high-speed link by writing its identification number to the EXTFSEL bit of the Microprocessor Extract FIFO Control register. A logic 0 selects the RXD1+/- FIFO while a logic 1 selects the RXD2+/- FIFO. 3. Read the header of the cell to determine if it is the end of message and to which virtual channel it belongs. 4. If CRC-32 protection is required, set the EXTCRCPR of the Microprocessor Extract FIFO Control and Status register to logic 0 to enable the CRC-32 process. The Extract CRC-32 accumulation register can be preset for the first cell of a message by writing a logic 1 to EXTCRCPR prior to enable the CRC32 calculation. If the cell is not the first one of a message and does not belong to the same control channel as the previous cell read, initialize the Extract CRC-32 Accumulator registers to the value saved from the previous cell read for the control channel. CRC-32 field check is done by setting the EXTCRCCHK bit of the Microprocessor Extract FIFO Control register to logic 1. This causes the
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S/UNI-DUPLEX to verify that the content of the CRC-32 Accumulator register is equal to the expected CRC-32 remainder polynomial when the last byte of the cell is read from the Extract FIFO. The microprocessor can verify the CRC-32 field check result either through interrupt servicing or polling techniques. When interrupt servicing is used, the microprocessor enables the CRC-32 field check prior to reading the last cell of the CPCS-PDU. An interrupt is raised if a CRC-32 error is found and the EXTCRCERRE bit is set. When polling is used, the EXTCRCERRE bit is kept to logic 0 and CRC-32 field check is always enabled. The microprocessor verifies the value of the EXTCRCERRI bit after reading the last cell of a CPCS-PDU. 5. Read the cell content from the Microprocessor Cell Data register. Cell data is extracted in the format illustrated in Fig. 11. 6. If the cell is not the last of the message, read and store the content of the Extract CRC-32 Accumulator register. This step is not necessary if the next cell extracted is known to belong to the same control channel as the current cell. The above sequence is repeated as needed to read more cells. The assertion of the bit of EXTRDY[1:0] of an Extract FIFO indicates that the FIFO is ready again to be read from. Setting EXTABRT of the Extract FIFO Control register to logic 1 allows the microprocessor to discard a cell without reading the remaining content.
12.2 Interaction Between Bus and LVDS Configurations
Since the far-end and near-end devices are configured independently it is important to take into account how the optional fields (the Any-PHY address field, the H5 (H5/UDF) header bytes, and the user prepend word) are treated on an end-to-end basis. The following table summarizes the possible cell format options and summarizes the resultant impact on the cell contents at the receiving end. Note the following:
*
The S/UNI-DUPLEX's LVDS links will be connected to other S/UNI-DUPLEX or to S/UNI-VORTEX devices. The following tables identify registers appropriate for a S/UNI-DUPLEX to S/UNI-DUPLEX connection. The results are similar for a S/UNI-DUPLEX to S/UNI-VORTEX. The S/UNI-VORTEX supports a more limited number of configurations (it does not support 8-bit
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parallel bus, master bus mode or clocked serial data). Refer to the S/UNIVORTLEX datasheet for details.
*
The parallel bus of the S/UNI-DUPLEX is fully compliant to Utopia Level 2 bus protocol only when configured as a bus master. In this case, cell length is either 53 bytes or 27 16-bit words depending if the interface bus width is set to 8 or 16 bit. When used as a bus slave, the parallel bus input and output ports can operate in SCI-PHY or Any-PHY mode. When configured as a SCI-PHY bus slave, the input port can be remains compliant to Utopia Level 2 (default setting), but the output port becomes a proxy, a single addressable PHY carrying the cell traffic for up to the 32 PHYs. The PHY ID is encoded in a system prepend byte or 16-bit word (depending if the interface bus width is set to 8 or 16 bit). To keep the cell compatible with Utopia Level 2 format, the PHY ID can be routed in the H5 (H5/UDF for 16-bit bus) field of the cell by setting the INADDUDF bit of the SCI-PHY/Any-PHY Output Configuration register to logic 1. When operating in SCI-PHY (master or slave mode) or in Any-PHY slave mode, prepend words can be added to the cell, up to two bytes for the 8-bit (PRELEN[1:0]=0b10) cell format and one word in 16-bit (PRELEN[1:0]=0b01) cell format. The H5 (H5/UDF) field of the cell can be omitted as determined by setting the H5UDF of the SCI-PHY/Any-PHY Input Configuration 1 and SCI-PHY/Any-PHY Output Configuration registers to logic 0. Both input and output parallel interface can operate in Any-PHY mode, meaning Any-PHY bus timing and addressing must be used. Setting the INADDUDF bit of the register SCI-PHY/Any-PHY Output Configuration register to 1 when the bus is configured as Any-PHY has no effect. Although the S/UNI-DUPLEX only supports 32 logic channels, it is possible to specify the base address of the input port in a larger addressing range with the Extended Address Match and Extended Address Mask registers. The value of the Extended Address Match register is also appended to the PHY ID of cells read from the output port. For a given configuration set by the values of the H5UDF, INADDUDF and PRELEN[1:0], cell length may vary depending of the mode of the parallel bus, determined by the value of the IMASTER, IBUS8, IANYPPHY, OMASTER, OBUS8 and OANYPHY inputs. The following is an example of the various cell lengths produced by the input port default configuration (H5UDF=1, PRELEN[1:0]=00): SCI-PHY/Utopia 8-bit master: 53B SCI-PHY/Utopia 8-bit slave: 53B Any-PHY 8-bit slave: 54B (base cell + address)
*
*
*
*
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SCI-PHY/Utopia16-bit master: 54B (base cell + UDF) SCI-PHY/Utopia16-bit slave: 54B (base cell + UDF) Any-PHY 16-bit slave: 56B (base cell + UDF + 2 address) The similar output port default configuration produces the following cell lengths: SCI-PHY/Utopia 8-bit master: 53B SCI-PHY 8-bit slave: 54B (base cell + address) Any-PHY 8-bit slave: 54B (base cell + address) SCI-PHY/Utopia16-bit master 54B (base cell + UDF) SCI-PHY16-bit slave: 56B (base cell + 2 address) Any-PHY16-bit slave: 56B (base cell + UDF + 2 address) In Table 19 to Table 23, these would be referred as 53/53/54(54/54/56) and 53/54/54(54/54/56) byte bus length.
*
When the input side is configured as a 8-bit parallel bus or as a clocked serial data interface and the output side is configured as a 16-bit parallel bus, the UDF is undefined at the far end independently of the LVDS link configuration. When the input side is configured as a 16-bit parallel bus and the output side is configured as a 8-bit parallel bus or as a clocked serial data interface, the UDF is stripped at the far end. When using the CSD (Clock Serial Data interface), the cell size is fixed at 53 bytes. By default, cell delineation is enable on the Clocked Serial Data receive port (Receive Serial Indirect Channel Configuration register 0x69, DDELIN=0). The HCS value is used only to acquire and maintain cell delineation and does not need to be carried to the other side. Similarly, by default the HCS value is generated by the Clock Serial Data transmit interface (Transmit Serial Indirect Channel Data register 0x71, DHCS=0) and does need to be carried over the LVDS link. When unframed data is transported through the Clocked Serial Data interface, data is packet in 53 byte packet and carried transparently. All five fields of the cell header are used and must be carried. For control cells written or read via the microprocessor port, bytes 0&1 correspond to the microprocessor port's unique PHY address field. However since this field is fixed there is no useful information in these bytes. Bytes 10&11 are always undefined. Bytes 2&3 correspond to the user prepend bytes, and bytes 8&9 correspond to the H5&HDF bytes. The PHY address field is transported across the LVDS in an extra word added to each user cell. Therefore it is not necessary that the H5 (H5/UDF) field be sent over the LVDS link even if the output bus interfaces is configured to embed the PHY address in the H5 (H5/UDF) field. This will slightly increase the effective throughput of the LVDS, but it will impact control
*
*
*
*
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cells inserted and extracted via the microprocessor port as described in section 12.1.
*
Many valid combinations are not shown in Table 19 to Table 23. Some of the missing combinations are readily derived from the table. Other combinations make little sense. For example, there is no use sending prepend information over the LVDS link if the receiving bus is not configured for prepends. Even if the near-end bus is configured for prepend it is more bandwidth efficient to turn off prepend on the LVDS link (the default setting) and hence discard the prepend at the near-end bus interface.
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Table 19 LVDS Link 59 Byte Cell Configurations
Far-End
input Reg 0x0C
Near-End
output Reg 0x14
Resultant Cell contents at far-end Bus or Microprocessor
LVDS: both ends must match e.g. Reg 0x40, 0x50 and 0x60
S C I A N Y
H 5 U D F
P R E L E N [1 .. 0] 0
S C I A N Y
H 5 U D F
I N A D D U D F 0
P R E L E N [1 .. 0] 0
DEFAULT CONFIGURATION 5 system, 6 header bytes, 48 data bytes USRHDR: 6 PREPEND: 0 CELLCRC: 0 * Control cell prepend bytes 2&3 are undefined, header bytes 8&9 are valid at far-end microprocessor.
*
1
1
1
1
* *
0
X
X
1
1
0
0
* *
1
1
0
0
X
X
0
* *
1
0
0
1
X
1
0
* *
1
1
0
1
X
1
0
* * *
0
X
X
1
X
1
0
* *
Cells are transferred from a 53/53/54(54/54/56) byte bus to a 53/54/54(54/56/56) byte bus. H5/UDF byte(s) is (are) valid, and there is no cell prepend other than the PHY address if Any-PHY is used. Cells are transferred from the CSD receive port and a 53/54/54(54/56/56) byte bus. The content of H5 is output at the far-end, UDF is undefined if present. Cells are transferred from a 53/53/54(54/54/56) byte bus to the CSD transmit port. If DHCS=0, H5 is passed transparently. If DHCS=1, it is replaced by the calculated HCS value. THIS CONFIGURATION IS VALID ONLY IF OMASTER=0 AND OANYPHY=0 AT THE FAR END DEVICE. Cells are transferred from a 52/52/53(52/52/54) byte bus to a XX/53/XX(XX/54/XX) byte bus (SCI-PHY slave only). Neither an address field nor a cell prepend exist. The PHY address is contained in H5 (H5/UDF). THIS CONFIGURATION IS VALID ONLY IF OMASTER=0 AND OANYPHY=0 AT THE FAR END DEVICE. Cells are transferred from a 53/53/54(54/54/56) byte bus to a XX/53/XX(XX/54/XX) byte bus (SCI-PHY slave only). Near-end H5 (H5/UDF) is stripped. Neither an address field nor a cell prepend exist. The PHY address is contained in H5 (H5/UDF). THIS CONFIGURATION IS VALID ONLY IF OMASTER=0 AND OANYPHY=0 AT THE FAR END DEVICE. Cells are transferred from the CSD receive port to a XX/53/XX(XX/54/XX) byte bus (SCI-PHY slave only). Neither an address field nor a cell prepend exist. The PHY address is contained in the H5 (H5/UDF).
Table 20 LVDS Link 58 Byte Cell Configurations
Far-End Near-End Resultant Cell contents at far-end Bus or Microprocessor
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input Reg 0x0C
output Reg 0x14
LVDS: both ends must match e.g. Reg 0x40, 0x50 and 0x60
S C I A N Y
H 5 U D F
P R E L E N [1 .. 0] 0
S C I A N Y
H 5 U D F
I N A D D U D F 0
P R E L E N [1 .. 0] 0
DEFAULT CONFIGURATION 5 system, 6 header bytes, 48 data bytes USRHDR: 5 PREPEND: 0 CELLCRC: 0 * Control cell prepend bytes 2&3 are undefined and header byte 9 bytes are undefined at the far-end microprocessor. Header byte 8 is defined.
* * *
1
1
1
1
0
X
X
1
1
0
0
* *
1
1
0
0
X
X
0
* *
1
0
0
1
X
1
0
* *
1
1
0
1
X
1
0
* * *
0
X
X
1
X
1
0
* *
Cells are transferred from a 53/53/54(54/54/56) byte bus to a 53/54/54(54/56/56) byte bus. The content of H5 is output at the far-end, UDF is stripped/undefined if present. There is no cell prepend other than the PHY address if Any-PHY is used. Cells are transferred from the CSD receive port and a 53/54/54(54/56/56) byte bus. The content of H5 is output at the far-end, UDF is undefined if present. Cells are transferred from a 53/53/54(54/54/56) byte bus to the CSD transmit port. If DHCS=1, H5 is passed transparently. If DHCS=0, it is replaced by the calculated HCS value. THIS CONFIGURATION IS VALID ONLY IF OMASTER=0 AND OANYPHY=0 AT THE FAR END DEVICE. Cells are transferred from a 52/52/53(52/52/54) byte bus to a XX/53/XX(XX/54/XX) byte bus (SCI-PHY slave only). Neither an address field nor a cell prepend exist. The PHY address is contained in H5 (H5/UDF). THIS CONFIGURATION IS VALID ONLY IF OMASTER=0 AND OANYPHY=0 AT THE FAR END DEVICE. Cells are transferred from a 53/53/54(54/54/56) byte bus to a XX/53/XX(XX/54/XX) byte bus (SCI-PHY slave only). Near-end H5 (H5/UDF) is stripped. Neither an address field nor a cell prepend exist. The PHY address is contained in H5 (H5/UDF). THIS CONFIGURATION IS VALID ONLY IF OMASTER=0 AND OANYPHY=0 AT THE FAR END DEVICE. Cells are transferred from the CSD receive port and a XX/53/XX(XX/54/XX) byte bus (SCI-PHY slave only). Neither an address field nor a cell prepend exist. The PHY address is contained in H5 (H5/UDF).
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Table 21 LVDS Link 57 Byte Cell Configurations
Far-End
Reg 0x0C
Near-End
Reg 0x14
Resultant Cell contents at far-end Bus or Microprocessor
LVDS: both ends must match e.g. Reg 0x40, 0x50 and 0x60
S C I A N Y
H 5 U D F
P R E L E N [1 .. 0] 0
S C I A N Y
H 5 U D F
I N A D D U D F 0
P R E L E N [1 .. 0] 0
DEFAULT CONFIGURATION 5 system, 6 header bytes, 48 data bytes USRHDR: 4 PREPEND: 0 CELLCRC: 0 * Control cell prepend bytes 2&3 and header bytes 8&9 are undefined at far-end microprocessor.
*
1
1
1
1
*
1
0
0
1
0
0
0
0
X
X
1
1
0
0
1
1
0
0
X
X
0
1
0
0
1
X
1
0
1
1
0
1
X
1
0
Cells are transferred from a 53/53/54(54/54/56) byte bus to a 53/54/54(54/56/56) byte bus. * H5 (H5/UDF) exists but is undefined at the far end bus. There is no cell prepend other than the PHY address if Any-PHY is used. * Cells are transferred from a 52/52/53(52/52/54) byte bus to a 52/52/53(52/52/54) byte bus. * There is no cell H5 (H5/UDF) or prepend other than the PHY address if Any-PHY is used. CAN NOT BE USED FOR CLOCKED SERIAL DATA CLEAR CHANNEL MODE * Cells are transferred from the CSD receive port to a 53/54/54(54/56/56) byte bus. * H5 (H5/UDF) is undefined at the far end. CAN NOT BE USED FOR CLOCKED SERIAL DATA CLEAR CHANNEL MODE * Cells are transferred from a 53/53/54(54/54/56) byte bus to the CSD transmit port. * H5 is not transported and must be generated at the transmit interface (DHCS=0). THIS CONFIGURATION IS VALID ONLY IF OMASTER=0 AND OANYPHY=0 AT THE FAR-END DEVICE. * Cells are transferred from a 52/52/53(52/52/54) byte bus to a XX/53/XX(XX/54/XX) byte bus (SCI-PHY slave only). * Neither an address field nor a cell prepend exist. The PHY address is contained in H5 (H5/UDF). THIS CONFIGURATION IS VALID ONLY IF OMASTER=0 AND OANYPHY=0 AT THE FAR-END DEVICE. * Cells are transferred from a 53/53/54(54/54/56) byte bus to a XX/53/XX(XX/54/XX) byte bus (SCI-PHY slave only). * Near-end H5 (H5/UDF) is stripped. * Neither an address field nor a cell prepend exist. The PHY address is contained in H5 (H5/UDF).
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0
X
X
1
X
1
0
* *
1
0 o r 1
0 o r 2
1
1
0
1
* *
THIS CONFIGURATION IS VALID ONLY IF OMASTER=0 AND OANYPHY=0 AT THE FAR END DEVICE. CAN NOT BE USED FOR CLEAR CHANNEL MODE Cells are transferred from the CSD receive port to a XX/53/XX(XX/54/XX) byte bus (SCI-PHY slave only). Neither an address field nor a cell prepend exist. The PHY address is contained in H5 (H5/UDF). Cells are transferred from a 52 to 58 byte bus to a 54/54/55(56/58/58) byte bus. At far-end the prepend(s) and H5 (H5/UDF) fields are undefined. Word 0 contains the PHY address in SCIPHY slave and Any-PHY mode
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Table 22 LVDS Link 61 Byte Cell Configurations
Far-End
input Reg 0x0C
Near-End
output Reg 0x14
Resultant Cell contents at far-end Bus or Microprocessor
LVDS: both ends must match e.g. Reg 0x40, 0x50 and 0x60
S C I A N Y
H 5 U D F
P R E L E N [1 .. 0] 2
S C I A N Y
H 5 U D F
I N A D D U D F 0
P R E L E N [1 .. 0] 1
DEFAULT CONFIGURATION 5 system, 2 prepend, 6 header and 48 data bytes USRHDR: 6 PREPEND: 1 CELLCRC: 0 * Control cell prepend bytes 2&3 and header bytes 8&9 are valid at far-end microprocessor.
*
1
1
1
1
* * * * * * *
1
1
2
1
1
0
2
* *
1
1
2
1
1
0
1
* * *
1
1
1
1
1
0
2
* *
NEAR-END IBUS8=1, FAR-END OBUS8=1 Cells are transferred from a 54/54/55(XX/XX/XX) byte bus to a 54/55/55(XX/XX/XX) byte bus. Prepend and H5 bytes are valid. NEAR-END IBUS8=1, FAR-END OBUS8=0 Cells are transferred from a 54/54/55(XX/XX/XX) byte bus to a XX/XX/XX(56/58/58) byte bus. Prepend MSB and H5 bytes are valid. Prepend LSB and UDF bytes are undefined. NEAR-END IBUS8=0, FAR-END OBUS8=1 Cells are transferred from a XX/XX/XX(56/56/58) byte bus to a 54/55/55(XX/XX/XX) byte bus. Prepend and H5 bytes are valid. NEAR-END IBUS8=0, FAR-END OBUS8=0 Cells are transferred from a XX/XX/XX(56/56/58) byte bus to a XX/XX/XX(56/56/58) byte bus. Prepends and H5/UDF bytes are valid. THIS CONFIGURATION IS VALID ONLY IF NEAR-END IBUS8=0 AND THE FAR-END OBUS8=1 Cells are transferred from a 55/55/56(XX/XX/XX) byte bus to a 55/56/56(XX/XX/XX) byte bus. Prepend (2 bytes) and H5 bytes are valid. THIS CONFIGURATION IS VALID ONLY IF NEAR-END IBUS8=1 Cells are transferred from a 55/55/56(XX/XX/XX) byte bus to a 54/55/55(56/58/58) byte bus. Prepend (2 bytes) and H5 bytes are valid. UDF undefined if used. THIS CONFIGURATION IS VALID ONLY IF NEAR-END OBUS8=1 Cells are transferred from a 54/54/55(56/56/58) byte bus to a 55/56/56(XX/XX/XX) byte bus. Prepend (2 bytes) and H5 bytes are valid.
Table 23 LVDS Link 59 Byte Cell Configurations with CRC
Far-End Near-End Resultant Cell contents at far-end Bus or Microprocessor
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input Reg 0x0C
output Reg 0x14
LVDS: both ends must match e.g. Reg 0x40, 0x50 and 0x60
S C I A N Y
H 5 U D F
P R E L E N [1 .. 0] 0
S C I A N Y
H 5 U D F
I N A D D U D F 0
P R E L E N [1 .. 0] 1
DEFAULT CONFIGURATION 5 system, 2 prepend, 4 header and 48 data bytes USRHDR: 4 PREPEND: 1 CELLCRC: 1 * Control cell prepend byte 2 is carried as is, but prepend byte 3 is overwritten with the CRC8. Header bytes 8&9 are undefined.
* * *
1
1
1
1
1
X
X
1
1
0
1
* *
1 1
1 1
1 0
0 1
X X
X 1
X 1
*
* *
*
Cells are transferred from a 53/53/54(54/54/56) byte bus to a 54/55/55(56/58/58) byte bus. At far-end the prepend and H5/UDF fields are all present. The first byte the prepend is undefined, the second byte contains the CRC8 from the previous cell. H5 (H5/UDF) is undefined. Cells are transferred from the CSD receive port to a 54/55/55(56/58/58) byte bus. At far-end the prepend and H5/UDF fields are all present. The first byte the prepend is undefined, the second byte contains the CRC8 from the previous cell. H5 (H5/UDF) is undefined Cells are transferred from a 54/54/55(56/56/58) byte bus to the CSD transmit port. THIS CONFIGURATION IS VALID ONLY IF OMASTER=0 AND OANYPHY=0 AT THE FAR-END. Cells are transferred from a 53/53/54(54/54/56) byte bus to a XX/54/XX(XX/56/XX) byte bus (SCI-ANY slave only). At far-end the prepend(s) and H5(H5/UDF) fields are all present. The first byte the prepend is undefined, the second byte (OBUS8=0) contains the CRC8 from the previous cell. At far-end the H5 (H5/UDF) field contains the PHY address.
12.3 Maximum Cell Bit Rate
The maximum cell bit rate transferred over the LVDS link is a function the LVDS bit rate and the ratio of transport overhead (system prepend & unused user defined field) versus cell data. Since the system prepend is fixed at 5 bytes, the absolute maximum throughput is achieved when the cell length is 56 bytes, i.e. the transported cells included 2 prepend bytes, H5 and UDF. Ratiomax = 56/61 = 91.8%, CellBRmax = 91.8% * 200 = 183.6 Mb/s Ratiomin = 52/61 = 85.2%, CellBRmin = 85.2% * 200 = 170.5Mb/s
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In addition to the LVDS stream capacity, the total Clocked Serial Data interface throughput is limited by the aggregate number of clock actives edges of all lines in each direction, independently of the idle and discarded cells. The instantaneous aggregate bit rate of all clocked serial data receive lines (including idle and discarded cells) has to be equal or less than the LVDS bit rate.
12.4 Minimum Programming
Besides the bus configuration described in the previous section, very little configuration is required to make the part function. The S/UNI-DUPLEX can operate in SCI-PHY/Utopia master mode or in Clocked Serial Data without external intervention. In addition to the registers described below, the following bit is commonly modified: 1. MINTE bit of the Master Configuration register (0x001) - This bit must be logic 1 to enable interrupt servicing. If MINTE is logic 0, the INTB output will be unconditionally high-impedance. Note that individual interrupt sources must enabled in addition to setting MINTE. The following three sections apply when operating the S/UNI-DUPLEX in parallel bus mode (SCIANY=1).
12.4.1 SCI-PHY/Utopia Master Mode
Although the default setting allows cell traffic to go, system performances may be improved by modifying the following registers. 1. PHYID[5:0] bits SCI-PHY/Any-PHY Input Configuration 2 and SCIPHY/Any-PHY Output Polling Range registers (0x0D, 0x15) - These bits are used to define the polling range of the SCI/PHY/Any-PHY input and output interface. 2. Input Cell Available Enable registers (0x10, 0x11, 0x12 and 0x13) - These registers can be used to dynamically remove PHYs from in the input port polling list. Setting a bit of these registers to logic 0 removes the corresponding PHY ID from the polling list.
12.4.2 SCI-PHY Slave
1. Output Address Match register (0x0A) - This register is used to set the proxy PHY ID for selection and transfer of cells on the SCI-PHY/Any-PHY output interface. 2. OCAEN bit of the Master Configuration register (0x001) - This bit must be a logic 1 before the OCA output responds to polling.
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12.4.3 Any-PHY Slave
In addition to the register required for the SCI-PHY slave, the following registers may need to be set at configuration 1. Extended Address Match and Extended Address Mask registers (0x06, 0x07, 0x08 and 0x09) - These registers are used to define the base address of the ANY-PHY input port. Cells are accepted by the S/UNIDUPLEX if the value in the Extended Address field of Word 0 agrees with the Extended Address Match registers over the range of bits specified by the Extended Address Mask registers. The value of the Extended Address Match registers content is also appended to the PHY ID of cells output on the Any-PHY output port.
12.4.4 Clocked Serial Data Interface
This sections applies when operating the S/UNI-DUPLEX in clocked serial data mode (SCIANY=0). 1. LTXCINV and LRXCINV of Master Configuration register (0x01)- Select the active edge of the receive and transmit serial clocks. The falling edge of LTXC[15:0] is used when to LTXCINV is set to logic 1. The falling edge of LRXC[15:0] is used when to LRXCINV is set to logic 1. 2. Transmit Logical Channel FIFO Depth register (0x5C) - This register control the DEPTH of the FIFO associated with cell traffic output on the LVDS links. By default, the FIFO is configured as a 32x2 cell FIFO to support the parallel bus configuration. The FIFO can be reconfigured as 16x4 cell FIFO by writing a value of 04 in register 0x5C. This maximizes system performances by allowing longer traffic bursts at the Clocked Serial Data receive interface. 3. DDELIN bit of the Receive Serial Indirect Channel Configuration register (0x69) and DHCS bit of the Transmit Serial Indirect Channel Data register (0x71) - These bits allow carrying raw data (arbitrary stream format) through the Clocked Serial Data interface. When DDELIN is set to logic 1, the RTTC does not perform any processing on the incoming stream, but passes data through transparently. Similarly when DHCS is logic 1, the fifth byte of the cell passes through the Clocked Serial Data transmit port unmodified. Both bits are written and read through indirect access by first selecting the serial channel by writing the CHAN[3:0] bits to the Receive Serial Indirect Channel (0x68)Select or the Transmit Serial Indirect Channel Select (0x70). Writing a logic 0 to CRWB of the same registers triggers an indirect write operation. Writing a logic 1 to CRWB of the same registers triggers an indirect read operation.
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4. ALIGN bit of the Transmit Serial Alignment Control register (0x74) - This bit allows ATM/DATA octet alignment to frame boundaries based on recognizing gaps in the transmit serial clock. When this bit is set to logic 1, the ATM /Data octets are aligned to the inferred frame alignment, with the most significant bit output first during the clock gap on all sixteen transmit channels.
12.4.5 Redundant Link Management
Upon power up, the S/UNI-DUPLEX is configured to automatically select the active LVDS link based on the value of the ACTIVE bit extracted from the LDVS receive links. It is also possible to externally control the selection process with the following register bits. 1. RXAUTOSEL and ACTIVE bits of the Master Configuration register (0x01) - When RXAUTOSEL is set to logic 1 (default value) the active LVDS serial link selection is done based on the value of the ACTIVE bit extracted from the receive high-speed data streams. When RXAUTOSEL is set tot logic 0, the active LVDS serial link is determined by the value of the ACTIVE bit. A logic 0 sets the link 1 (RXD1+/-) active, a logic 1 sets the link 2 (RXD2+/-) active. Since link switching is performed on cell boundaries, a delay may happen between writing a new ACTIVE bit value and reading back its value.
12.5 JTAG Support
The S/UNI-DUPLEX supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standard. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown in Fig. 16.
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Fig. 16 Boundary Scan Architecture
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a singlebit delay from primary input, TDI to primary output, TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register place in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be
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sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital outputs.
TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is illustrated in Fig. 17.
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Fig. 17 TAP Controller Finite State Machine
TRSTB=0 Test-LogicReset 1 0 Run-TestIdle 1 Select-DRScan 0 1 CaptureDR 0 ShiftDR 1 Exit1DR 0 PauseDR 1 0 Exit2DR 1 UpdateDR 1 0 0 0 0 1 1 1 Select-IRScan 0 CaptureIR 0 ShiftIR 1 Exit1IR 0 PauseIR 1 Exit2IR 1 UpdateIR 1 0 0 0 1 1
0
All transitions dependent on input TMS
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Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction.
Run-Test-Idle
The run test/idle state is used to execute tests.
Capture-DR
The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK.
Shift-DR
The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
Update-DR
The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK.
Capture-IR
The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK.
Shift-IR
The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
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Update-IR
The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused.
12.5.1 Boundary Scan Instructions
The following is an description of the standard instructions. Each instruction selects an serial test data register path between input, TDI and output, TDO.
BYPASS
The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device.
EXTEST
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is place between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state.
SAMPLE
The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state.
IDCODE
The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state.
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STCTEST
The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out output, TDO using the Shift-DR state.
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13
FUNCTIONAL TIMING
While the following diagrams present representative waveforms, they are not an attempt to unambiguously describe the interfaces. The Pin Description is intended to denote the detailed pin behavior and constraints on use.
13.1 SCI-PHY/Any-PHY Interface
Fig. 18 is an example of the functional timing of the SCI-PHY/Any-PHY Interface when configured as a 16-bit SCI-PHY Level 2 compliant input bus slave. "A", "B", "C" and "D" represent any arbitrary address values out of the 32 possible SCI-PHY addresses. Since up to 32 PHY devices can reside on the SCI-PHY bus, the bus master can poll PHY "1Fh", provided that IAVALID signal is used. The polls of logical channels "B" and "C" illustrate that polls in consecutive cycles are permitted. Once a logic high is returned on ICA in response to a poll, a cell may be transferred. The transfer can be paused by deasserting IENB. The logical channel "A" is reselected before the transfer resumes.
Fig. 18 SCI-PHY Interface, Input Bus Slave Transfer Timing
IFCLK IDAT[15:0] IADDR[4:0] IAVALID IENB ICA ISOC
CH A W 23 W 24 W 25 W 26 W 27 XX X W0 W1 W2 XX X XX X W3
1F h
IFh
A
1F h
1F h
A
1F h
B
C
XX
A
D
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DUAL SERIAL LINK PHY MULTIPLEXER
Fig. 19 gives an example of the functional timing of the SCI-PHY/Any-PHY Interface when configured as a 16-bit SCI-PHY Level 2 compliant input bus master. When polling PHY devices, the S/UNI-DUPLEX inserts null cycles by deasserting the IAVALID output and forcing the IADDR[4:0] bus to "1Fh" to prevent bus contention. Once a ready to transfer PHY is found (PHY at address "C" in this example), its address is maintained on the address bus till the current transfer is completed. The PHY is then selected and the transfer initiated. The S/UNI-DUPLEX transfers the complete cell without pause.
Fig. 19 SCI-PHY Interface, Input Bus Master Transfer Timing
IFCLK IDAT[15:0] IADDR[4:0] IAVALID IENB ICA ISOC
CH C W 20 W 21 W 22 W 23 W 24 W 25 W 26 XXX XXX W0 W1
A
IFh
B
1F h
C
1F h
C
1Fh
D
1F h
Fig. 20 gives an example of the functional timing of the of the SCI-PHY/Any-PHY Interface when configured as a 16-bit Any-PHY compliant input bus slave. In this example, the IAVALID pin is used as the IADDR[5] line of the IADDR[5:0] bus (the null address becomes 3Fh) and the Extended Address register is unused.The polls of logical channels "A", "B" and "C" illustrate that polls in consecutive cycles are permitted. The S/UNI-DUPLEX responds to polling of logical channel "D" by asserting ICA high on the second following clock cycle. Logical channel "D" is selected by the bus master assertion of ISX and a cell transfer is initiated. The IENB input is not required to be deasserted at the end of a cell transfer. Upon completion of the cell transfer, the interface autonomously deselects itself. The transfer can be paused by deasserting IENB. The cell transfer from the same logical channel resumes immediately when IENB is reasserted low.
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Fig. 20 Any-PHY Interface, Input Bus Slave Transfer Timing
IFCLK IADDR[5:0] ICA IENB IDAT[15:0] IPRTY IS X
W 24 W 25 W 26 W 27 XX X XX X XX X CH D W1 W2 W3 XX X XX X W3 A B C 3F h D 3F h A 3F h B 3F h C 3F h 3F h A
XX X
XX X
XX X
XX X
XX X
Fig. 21 is an example of the functional timing of the SCI-PHY/Any-PHY Interface when configured as a 8-bit SCI-PHY Level 2 compliant output bus slave. In this example, address "A" corresponds to the content of the Output Address Match register of the S/UNI-DUPLEX. The SCI-PHY/Any-PHY Output Interface acts a proxy for its 32 logical channels. Once it returns a logic high on OCA in response to a poll, a cell may be transferred. The logical channel ID is output as the first word of the cell, its most significant bits derived from the contents of the Extended Address Match registers. The transfer can be paused by deasserting OENB. The interface must be reselected before the transfer can resume.
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Fig. 21 SCI-PHY Interface, Output Bus Slave Transfer Timing
OFCLK OADDR[4:0] OAVALID OENB OCA ODAT[15:0] OPRTY OSOC
W 48 W 49 W 50 W 51 W 52 W 53 CH ID W0 W1 1F h A IFh A IFh A IFh B IFh C IFh D
Fig. 22 is an example of the functional timing of the SCI-PHY/Any-PHY Interface when configured as a 8-bit Utopia Level 2 compliant output bus master. The S/UNI-DUPLEX polls PHY devices round robin with OADDR[4:0] and OAVALID while performing a cell transfer. The PHY at address "A" responds to polling by asserting OCA high. Because of internal processing delays of the S/UNIDUPLEX interface, the polling process stops only after the address of next PHY of the round robin sequence is set on the bus. IADDR[4:0] value is reverted to the preceding polled PHY address until the cell transfer is completed. The S/UNI-DUPLEX selects PHY "A" for a cell transfer and resumes the round robin polling process.
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Fig. 22 SCI-PHY Interface, Output Bus Master Transfer Timing
OFCLK O ADDR[4:0] O AVALID O ENB OCA O DAT[15:0] O SOC
CH A
A
IFh
B
IFh
A
1F h
B
1F h
C
1F h
D
W 48
W 49
W 50
W 51
W 52
XXX
W0
W1
W2
W3
W4
W5
Fig. 23 is an example of the functional timing of the SCI-PHY/Any-PHY Interface when configured as a 16-bit Any-PHY compliant output bus slave. In this example, address "A" (since the Output Address Match register is 5 bit wide, the most significant bit is ignored) corresponds to the content of the Output Address Match register of the S/UNI-DUPLEX. In this example, OAVALID is used as the OADDR[5] line. OAVALID has to be logic low for a match to occur. The SCIPHY/Any-PHY output interface acts a proxy for its 32 logical channels. Once it returns a logic high on OCA in response to a poll, a cell may be transferred. Coincident with the OSX output, the logical channel ID is output as the first word of the cell, its most significant bits derived from the contents of the Extended Address Match registers. The OENB input is not required to be deasserted at the end of a cell transfer. Upon completion of the cell transfer, the interface autonomously deselects itself. The transfer can be paused by deasserting OENB. The cell transfer from the same logical channel resumes immediately when OENB is reasserted low.
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Fig. 23 Any-PHY Interface, Output Bus Slave Transfer Timing
OFCLK OADDR[4:0] OENB OCA ODAT[15:0] OSX OSOC
W 24 W 25 W 26 W 26 W 27 CH ID W1 W2 W3 A 3F h B 3F h A 3Fh B 3F h C 3Fh D
13.2 Clocked Serial Data Interface
The timing relationship of the transmit clock (LTXC[N]) and data (LTXD[N]) signals is shown in Fig. 24. The transmit data is viewed as a contiguous serial stream. Data bytes are transmitted from most significant bit to least significant bit. Bits are updated on the rising or falling edge of LTXC[N], as determined be the value of the LTXCINV bit of the Master Configuration register (in Fig. 24, LTXCINV is set to logic 0). A transmit link may be stalled by holding the corresponding LTXC[N] low.
Fig. 24 Clocked Serial Data Transmit Interface
LTXC[N] LTXD[N]
B[1] B[0] B[7] B[6] B[5] B[4] B[3] B[2]
When the ALIGN bit of the Transmit Serial Framing Bit Threshold register is set to logic 1, a clock gap longer that the minimum detectable period causes the most significant bit of the data octet to be output during the gap period. The S/UNI-DUPLEX can detect clock gaps of 8 line clock periods over the entire LTXC[15:0] clock line frequency range. The range of the frequency at which 1 bit framing gap can be detected changes linearly with the speed of the high-speed links. When operating the LVDS link at 200 Mb/s (REFCLK frequency set to 25 MHz), the S/UNI-DUPLEX will detect one bit clock gap for line frequency range of 200 kHz to 8 MHz.
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To be detected, the gap polarity must match the value of the LTXCINV bit of the Master Configuration register. When the rising edge of clock signals on LTXC[15:0] is used to output the data (LTXCINV set to logic 0), gaps during which the clock is forced to logic 0 are detected. In Fig. 25, bits are byte aligned to a 1 bit clock gap. When the falling edge of the clock signals on LTXC[15:0] are used to output the data (LTXCINV set to logic 1), gaps during which the clock is forced to logic 1 are detected. In Fig. 26, bits are output on the falling edge of the byte aligned to an 8 bit clock gap.
Fig. 25 Clocked Serial Data Transmit Interface, 1 Bit Gap
LTXC[N] LTXD[N]
B[1] B[0] B[7] B[6] B[5] B[4] B[3]
Fig. 26 Clocked Serial Data Transmit Interface, 8 Bit Gap
8 CLOCK PERIODS
LTXC[N] LTXD[N]
B[0] B[7] B[6] B[5]
The timing relationship of the receive clock (LRXC[N]) and data (LRXD[N]) signals is shown in Fig. 27. The receive data is viewed as a contiguous serial stream, with the most significant bit of the ATM/Data byte received first. Bits that are to be processed are clocked in either on the rising or falling edge of LRXC[N], determined by the value of the LRXCINV bit of the Master Configuration register. In Fig. 27, the rising edge of LRXC[N] is used. Bits that should be ignored ("X" in Fig. 27) are squelched by holding LRXC[N] low. When ATM cells are received, the S/UNI Duplex performs cell delineation on the received bits to recover byte alignment.
Fig. 27 Clocked Serial Data Receive Interface
LRXC[N] LRXC[N]
B[5] X X B[4] B[3] B[2] X B[1] X B[0] B[7] B[6] B[5]
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14
ABSOLUTE MAXIMUM RATINGS
Maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal mode operation conditions. Case Temperature under Bias Storage Temperature Supply Voltage Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Absolute Maximum Junction Temperature -40C to +85C -40C to +125C -0.5V to +6.0V -0.5V to VDD+0.5V 1000 V 100 mA 20 mA +300C +150C
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15 D.C. CHARACTERISTICS TA = -40C to +85C, VDD =3.3 V 10% (Typical Conditions: TC = 25C, VDD = 3.3 V) Symbol Parameter Min Typ Max Units Conditions
VDD VBIAS VIL VIH
Power Supply 5 V Tolerant Bias Input Low Voltage (TTL Only) Input High Voltage (TTL Only)
3 VDD -0.5 2.0
3.3 5.0
3.6 5.5 0.8 VBIA +0.5
S
Volts Volts Volts Volts Guaranteed Input LOW Voltage Guaranteed Input HIGH Voltage for, A[8:0], RDB, WRB, CSB, ALE, D[7:0], TX8K, REFCLK, TDI, TCK and TMS, Guaranteed Input HIGH Voltage for IENB, IADDR[4:0], IAVALID, IDAT[15:0], ISOC, ISX, ICA, IPRTY, IFCLK, OENB, OADDR[4:0], OAVALID, OCA, OFCLK, IANYPHY, OANYPHY, IMASTER, OMASTER, IBUS8, OBUS8, LRXD[15:0], LRXC[15:0], LTXC[15:0] and SCIANY. VDD = min, IOL = -2 mA minimum. Note 3
VIH
Input High Voltage (TTL Only)
2.0
VDD +0.5
Volts
VOL
Output or Bidirectional Low Voltage (TTL Only) Output or Bidirectional High Voltage (TTL Only) 2.4
0.1
0.4
Volts
VOH
3.0
Volts
VDD = min, IOH = 2 mA minimum. Note 3
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DUAL SERIAL LINK PHY MULTIPLEXER
Symbol
Parameter
Min
Typ
Max
Units Conditions
VT+
Reset Input High Voltage Reset Input Low Voltage Reset Input Hysteresis Voltage
2.0
VBIA +0.5 0.8 0.5
S
Volts
TTL Schmitt for RSTB and TRSTB RSTB and TRSTB RSTB and TRSTB
VTVTH
Volts Volts
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Symbol
Parameter
Min
Typ
Max
Units Conditions
VICM
LVDS Input Common-Mode Range LVDS Input Differential Sensitivity LVDS Input Differential Hysteresis LVDS Differential Input Impedance LVDS Output voltage high LVDS Output voltage low LVDS Output Differential Voltage LVDS Output Common-Mode Voltage LVDS Output Impedance, Single-Ended LVDS Output Impedance Mismatch between TXOP and TXON Change in |VODM| between "0" and "1" Change in VOCM between "0" and "1"
0
2.4
V
|VIDM|
100
mV
|VHYST|
25
mV
RIN VLOH VLOL VODM
10 1375 1475 925 250 1025 350 400
K mV mV mV RLOAD=100 1% RLOAD=100 1% RLOAD=100 1% Note 5
VOCM
1125 1200 1275
mV
RLOAD=100 1%
RO
70
130
VCM=1.0V and 1.4V
RO
10
%
VCM=1.0V and 1.4V
|VODM|
25
mV
RLOAD=100 1%
VOCM
25
mV
RLOAD=100 1%
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Symbol
Parameter
Min
Typ
Max
Units Conditions
ISP, ISN
LVDS ShortCircuit Output Current LVDS ShortCircuit Output Current Input Low Current Input High Current Input Low Current Input High Current Input Capacitance Output Capacitance Bidirectional Capacitance Operating Current Processing Cells +20 -10 -10 -10 +83 0 0 0 5 5 5
10
mA
Drivers shorted to ground
ISPN
10
mA
Drivers shorted together
IILPU IIHPU IIL IIH CIN COUT CIO IDDOP
+200 +10 +10 +10
A A A A pF pF pF
VIL = GND. Notes 1, 3 VIH = VDD. Notes 1, 3 VIL = GND. Notes 2, 3 VIH = VDD. Notes 2, 3 Excluding Package, Package Typically 2 pF Excluding Package, Package Typically 2 pF Excluding Package, Package Typically 2 pF VDD = 3.6 V, Outputs Unloaded, RXD1+/-, RXD2+/-, TXD1+/- and TXD2+/-200 Mb/s OFCLK = IFCLK = 52 MHz Note 4
450
mA
Notes on D.C. Characteristics:
1. Input pin or bi-directional pin with internal pull-up resistor. 2. Input pin or bi-directional pin without internal pull-up resistor 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. When IMASTER = OMASTER = 0 and SCIANY = 1. OFCLK = IFCLK = 33 MHz when IMASTER = OMASTER = 1. 5 When the device is in reset, the differential voltage is approximately 80 mV. Once the device is out of reset, the voltage returns to the normal level.
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16
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS (TA = -40C to +85C, VDD = 3.3 V 10%) Microprocessor Interface Read Access (Fig. 28) Symbol Parameter Min Max Units
tSAR tHAR tSALR tHALR tVL tSLR tHLR tPRD tZRD tZINTH
Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Latch to Read Hold Valid Read to Valid Data Propagation Delay Valid Read Negated to Output Tri-state Valid Read Negated to Output Tri-state
10 5 10 10 20 0 5 70 20 50
ns ns ns ns ns ns ns ns ns ns
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Fig. 28: Microprocessor Interface Read Timing
A[6:0] tS ALR tV L ALE tS AR (CSB+RDB)
Valid Address
tH ALR tS LR tHLR
tH A R
tZ INTH
tP RD D[7:0]
tZ RD
Valid Data
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point. 2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus, (D[7:0]). 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals. 4. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALR, tHALR, tVL, and tSLR are not applicable. 5. Parameter tHAR is not applicable if address latching is used. 6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
Microprocessor Interface Write Access (Fig. 29) Symbol Parameter Min Max Units
tSAW tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW tVWR
Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Set-up Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Valid Write Pulse Width
10 20 10 10 20 0 5 5 5 40
ns ns ns ns ns ns ns ns ns ns
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Fig. 29: Microprocessor Interface Write Timing
A[6:0] tS ALW tV L ALE tS AW (CSB+W RB)
Valid Address
tH ALW tS LW tHLW
tV W R
tH AW
tS DW D[7:0]
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing:
1 A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2 In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW , tHALW , tVL, and tSLW are not applicable. 3 Parameter tHAW is not applicable if address latching is used. 4 When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 5 When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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17
A.C. TIMING CHARACTERISTICS (TA = -40C to +85C, VDD = 3.3 V 10%) RSTB Timing (Fig. 30) Symbol Parameter Min Max Units
tVRSTB
RSTB Pulse Width
100
ns
Fig. 30: RSTB Timing
tV RSTB RSTB
REFCLK Timing Symbol Parameter Min Max Units
fREFCLK DREFCLK
REFCLK Frequency REFCLK Duty Cycle REFCLK Frequency Tolerance
12.5 20
25 80 100
MHz % ppm
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Ingress SCI-PHY/Any-PHY Interface (Fig. 31) Symbol Description Min Max Units
IFCLK Frequency (IMASTER = 0) IFCLK Frequency (IMASTER = 1) tSIFCLK tHIFCLK tPIFCLK tZIFCLK tZBIFCLK IFCLK Duty Cycle IDAT[15:0], IADDR[4:0], IPRTY, ISOC, IENB, IAVALID, ISX and ICA Set-up time to IFCLK IDAT[15:0], IADDR[4:0], IPRTY, ISOC, IENB, IAVALID, ISX and ICA Hold time to IFCLK IFCLK High to IENB, IADDR[4:0], IAVALID and ICA Valid IFCLK High to ICA High Impedance IFCLK High to ICA Driven
0 0 40 3 1 2 2 0
52 33 60
MHz MHz % ns ns
12 12
ns ns ns
Fig. 31: Ingress SCI-PHY/Any-PHY Interface Timing
IFCLK
tS IFCLK IDAT15:0] IPRTY, ISOC, ISX, ICA
tH IFCLK
IENB tP IFCLK IADDR[4:0] IAVALID tZ
IFCLK
Valid Data
Valid Data
tZB IFCLK ICA
tPIFCLK Valid Data
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Egress SCI-PHY/Any-PHY Interface (Fig. 32) Symbol Description Min Max Units
OFCLK Frequency (OMASTER = 0) OFCLK Frequency (OMASTER = 1) tSOFCLK tHOFCLK tPOFCLK OFCLK Duty Cycle OCA, OENB, OADDR[4:0] and OAVALID Set-up time to OFCLK OCA, OENB, OADDR[4:0] and OAVALID Hold time to OFCLK OFCLK High to OSOC, ODAT[15:0] OPRTY, OENB, OADDR[4:0], OAVALID and OCA Valid OFCLK High to Output High Impedance
0 0 40 3 1
52 33 60
MHz MHz % ns ns
tZOFCLK
2 2 0
12 12
ns ns ns
tZBOFCLK OFCLK High to Driven
Fig. 32: Egress SCI-PHY/Any-PHY Interface Timing
OFCLK
tS OFCLK OADDR[4:0] OAVALID tP OFCLK OENB tZ ODAT[15:0] OPRTY OSOC OSX, OCA Valid Data Valid Data
tH OF CLK
OF CLK
tZB OF CLK
tPOFCLK Valid Data
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Clocked Serial Data Interface (Fig. 33) Symbol Description Min Max Units
LTXC[N], LRXC[N] Frequency tSLRXD tHLRXD tPLTXD LTXC[N], LRXC[N] Duty Cycle LRXD[N] Set-up Time to LRXC[N] (see note) LRXD[N] Hold Time to LRXC[N] (see note) LTXC[N] to LTXD[N] Valid (see note) 40 8 5 1
52 60
MHz % ns ns ns
13
Note: Polarity of the active edge of LTXC[N] and LRXC[N] is determined by the respective value of the LRXCINV and LTXCINV bits in the Master Configuration register.
Fig. 33: Clocked Serial Data Interface
LRXC[N ]
tS LRXD
LRXD[N ]
tH LRXD
LTXC[N] tP LT XD LTXD[N]
High-Speed Serial Interface
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DUAL SERIAL LINK PHY MULTIPLEXER
Symbol
Description
Min
Max
Units
RXD1+/-, RXD2+/- Bit Rate tFALL tRISE tSKEW VODM fall time, 20%-80% VODM rise time, 20%-80% Differential Skew
8fREFCLK 8fREFCLK
-100ppm +100ppm
Mb/s ps ps ps
300 300
700 700 50
JTAG Port Interface (Fig. 34) Symbol Description Min Max Units
TCK Frequency tSTMS tHTMS tSTDI tHTDI tPTDO tVTRSTB TCK Duty Cycle TMS Set-up time to TCK TMS Hold time to TCK TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid TRSTB Pulse Width 40 50 50 50 50 2 100
4 60
MHz % ns ns ns ns
50
ns ns
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Fig. 34: JTAG Port Interface Timing
TCK tS TMS TMS tS TDI TDI tH TDI tH TMS
TCK tP TDO TDO
tV TRSTB TRSTB
Notes on Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
Notes on Output Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 50 pF load on the outputs with the exception of the LTXD[15:0], RX8K, RCLK outputs. The LTXD[15:0], RX8K, RCLK output propagation delays are measured with a 20 pF load
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
225
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
18
ORDERING AND THERMAL INFORMATION PART NO. PM7350-PI PART NO. PM7350-PI DESCRIPTION 160 Plastic Ball Grid Array (PBGA) CASE TEMPERATURE -40C to 85C Theta Ja 30 C/W Theta Jc - C/W
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
226
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
19
MECHANICAL INFORMATION
The S/UNI-DUPLEX comes in a 15 x 15 x 1.81 mm 160 PBGA (4 layer) package.
0.20 (4x) A1 B ALL P AD CO R NER A1 BA LL PA D CO RNE R B 14 12 10 8 6 4 2 13 11 9 7 5 3 1 A B C D E F G H J K L M N P "d" DIA. 3 PLACES
D D1
A
e
A1 BALL PAD INDICATO R
E1
E
45 CHAM FER 4 PLACES
J
TOP VIEW C A
30 TYP
I
b
BOTTOM VIEW
A1
A2
SEAT ING PLANE
SIDE VIEW
NO TES: 1) ALL DIM EN SIO NS IN M ILLIM ETER. 2) DIMENSION aaa DENO TES C OPLANA RITY. 3) DIMENSIO N bbb DE NO TES PARALLEL.
1.40 1.61 1.80
1.60 1.81 2.02
0.30 0.40 0.50
0.80 0.85 0.90
0.30 0.36 0.40
0.50 0.56 0.62 15.00
12.50 13.00 15.00 13.70
12.50 13.00 13.70 1.00 1.00 1.00
0.40 0.50 0.60 0.15 0.35
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
227
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
228
RELEASED DATA SHEET PMC-1980581 ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
CONTACTING PMC-SIERRA, INC.
PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2000 PMC-Sierra, Inc. PMC-980581 (R5) ref PMC-980169 (R5) Issue date: April 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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